As I/O standards continue to evolve towards serialization in both backplane and, more recently, chip-to-chip applications, high speed parallel I/O still has an important role in specific chip-to-chip applications in which current serial technologies are cost prohibitive.
Apart from established NPU, framer and module based source synchronous I/O standards such as SPI4.2, SFI4.1, XGMII, HyperTransport, Rapid IO and CSIX, the next generation of clock forwarded interfaces are being implemented on SRAM and DRAM memories (DDR1/2/3, RLDRAM1/2 and QDR2) as well as ADCs and DACs. The I/O speeds required for these next generation applications are expected to exceed 1Gbps.
FPGAs are being increasingly used as programmable SoCs, designed in as an integral part of the system data path. However, with this usage comes the expectation that these devices are capable of performing high-speed I/O translation and processing. As programmable ASSPs, there is also the expectation for compliance with past, existing and emerging I/O standards. Conversely, the inherent nature of FPGAs requires that they serve a broad base of applications, and so are not typically tuned to the highly sensitive requirements of specific source synchronous I/Os to the same degree as their ASSP and ASIC counterparts. The question becomes: how can this level of performance be achieved in an FPGA array, given its universal applicability and lack of specialization?
Although electrical compliance and high-speed signal integrity are required features, these alone do not address the bandwidth issue. The FPGA I/O must also have circuitry to manage and maintain the clock and data relationships of these high speed signals, as well as provide the necessary "gearbox" functionality in order to support the transfer of the high speed I/O data to the FPGA fabric to perform the desired processing functions.
FPGA vendors have tackled this problem in various ways, using pre-engineered, dedicated I/O circuitry to perform these specialized functions. The driving objective is to provide a transparent scheme that maximizes performance yet minimizes the need for board level tweaks, reducing development time and cost.
This white paper examines how the LatticeSC PURESPEED I/O architecture addresses these system level concerns by delivering the highest performing and most feature rich source synchronous I/Os of any existing or announced FPGA family, surpassing even its own previous best-in-class FPSC-based I/Os.
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