Delivering FPGA-Based Pre-engineered IP Using Structured ASIC Technology

Lattice has introduced a new silicon technology to meet today's ever-increasing demand for performance, density, low power and time-to-market. Called MACO, this technology adds a 90nm structured ASIC capability to an advanced FPGA + SERDES platform. The MACO gates provide superior density and performance with significantly lower power dissipation. MACO is ideal for industry-standard IP such as memory controllers, SPI4.2, and MACs that are necessary for today's communications design, but cannot be optimized in soft IP. This results in substantial development cost reduction because standards are committed to dedicated silicon and the FPGA gates are reserved for value-added and differentiating features.

MACO conserves power by implementing IP previously targeted for LUT-based architectures in 90nm cell-based technology. MACO blocks do not exceed 200mW per site, even at 700MHz performance. This type of power dissipation can't be matched in 90nm LUT architectures running at similar clock rates.

MACO conserves area by shrinking 5,000 equivalent LUTs into a much smaller silicon area. With multiple MACO blocks per device, this significantly boosts device density. Since MACO is ideal for industry-standard IP cores, this means that valuable LUT-based silicon is reserved for value-added design features.

Finally, MACO improves device performance. Since MACO is a 90nm cell-based technology like a structured ASIC, it is capable of > 700Mhz performance with little design effort. Ample connectivity is provided to connect each MACO to LatticeSCM I/O technology, as well as embedded RAM and programmable logic blocks.

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