Consequently, all major silicon and core Intellectual Property (IP) vendors now include on-chip silicon resources or core extensions to alleviate the difficulties facing developers of software for embedded systems based on such architectures. Such resources allow debug access to the core, and much of the functionality of traditional in-circuit emulators is thus enabled using a new breed of emulator which can access and control these on-chip debug resources.
In very many cases, the device's JTAG pins, normally used for boundary scan test purposes, are ‘hijacked' to allow access to the on-chip debug resource. Typical core IP examples include the products from ARM Ltd and MIPS Inc, which include EmbeddedICE and EJTAG on-chip debug facilities respectively, both accessed over JTAG. Motorola, for many years to the forefront in on-chip debug technology, offers BDM, OnCE, COP, Nexus and other debug schemes based on on-chip aids to emulation. Many other vendors, including Hitachi, ST Microelectronics, SuperH and Infineon, have developed similar on-chip debug facilities, not to mention the wide variety of semiconductor vendors whose devices include on-chip debug through licence arrangements with IP vendors such as the aforementioned ARM and MIPS.
Owing to the enormous popularity of the ARM cores, with 77 licensees shipping over 420 million ARM powered devices in 2001, the ARM on-chip debug facilities merit closer examination. This paper looks at the run-time control debug features provided ARM cores. ARM have also developed a core extension called the Embedded Trace Macrocell (ETM) which provides for the provision of compressed program and data trace information via a narrow port. ETM is currently available as a core extension for ARM7 and ARM9 products and will be covered in more detail in a future Ashling paper.
View Entire Paper | Previous Page | White Papers Search
If you found this page useful, bookmark and share it on: