Closing the Nanometer Yield Chasm

A whole new set of challenges awaits designers as they migrate to nanometer process technologies (0.25µm and below). Designers must overcome these challenges in their quest to produce high-quality, high-performance, and high-yielding designs. Design methodologies for digital ICs traditionally center on design validation—to ensure correct functionality and that the design satisfies timing and power requirements. The current generation of EDA tools and design techniques have evolved to analyze each of these metrics. However, these tools fail to address many of the key electrical effects that impact the yield of nanometer designs.

View Entire Paper | Previous Page | White Papers Search

If you found this page useful, bookmark and share it on:

 
Embedded Star Newsletter
Don't have time to visit Embedded Star everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.

Enter your email address to sign up for our free newsletter:   

If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.