Closing the Nanometer Yield Chasm

A whole new set of challenges awaits designers as they migrate to nanometer process technologies (0.25µm and below). Designers must overcome these challenges in their quest to produce high-quality, high-performance, and high-yielding designs. Design methodologies for digital ICs traditionally center on design validation—to ensure correct functionality and that the design satisfies timing and power requirements. The current generation of EDA tools and design techniques have evolved to analyze each of these metrics. However, these tools fail to address many of the key electrical effects that impact the yield of nanometer designs.

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