Article for Bus and Boards Europe

With the advent of high performance reduced instruction set chips (RISC) such as the Intel i860, popular in the early 1990s, and today's Power PC family, attention remains focused on using arrays of RISC chips for real-time DSP applications. This paper uses radar parameters typical of airborne early warning (AEW) applications as a means for showing the development process engineers follow, first to choose the chip family and then the board architecture that best fits an application.

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