For sub 0.18-micron VLSI technology, the interconnect has become a significant part of the timing delay in circuits. Therefore, it is very important to accurately predict the interconnect delay. At the same time, the feature sizes have become much smaller than the wavelength of the light source used in optical lithography. Optical distortions, which have traditionally been ignored due to the light wavelength being larger than the feature size, can no longer be ignored. These distortions create patterns on silicon that are substantially different from the drawn layout for the sub 0.18 micron technology using the 248 nm or higher wavelength light source. This paper investigates the effects of subwavelength lithography distortions on the accuracy of parasitic extraction. The idea is to figure out if we can continue using the drawn layout for parasitic extraction or we need to use the simulated aerial or silicon image instead.
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