A Foundation Architecture for Elevating DSP in FPGAs

Commonly Military equipment has always desired more performance from their systems than technology has been able to provide. This covers all areas from the defense systems themselves to the test equipment that is used to prove these systems. These systems require the processing of increasing data sets and accelerating bandwidth originating from applications such as radar, sonar and imaging. Additionally multi-sensor fusion further accentuates the increases in the data processing demands of modern systems.

Traditional DSP processor architectures have only been capable of performing low complexity image processing functions in real time and this is still the case even with the very latest DSP processors from the Texas Instruments and Analog Devices. Furthermore the relatively short life of any processor makes the DSP a less than ideal solution in military system.

The advent of the FPGA back in the late 80's shone a new light on to the data processing possibilities. Nallatech saw the growing capabilities of the FPGA and was one of the first adopters to build systems that harnessed the FPGA as a coprocessor to various DSPs and Microprocessors.

These ideas were demonstrated in HardWare In the Loop, HWIL, systems proving equipment. This early equipment was used to generate simulated 3D target imagery to test British Aerospace's Rapier Weapon systems. The FPGAs were initially used to perform simple Gain and Offset control and Filtering functions at the pixel processing level. This partitioning of multiple FPGAs and multiple Microprocessors in the system allowed Real Time Image processing functions at a very low latency to be achieved.

Through the 90's the FPGA's increased in capacity and speed thus redefining the partitioning of FPGAs and Processors enabling more of the heavy processing requirements normally performed on the DSP to be moved across to the FPGA. Also, HWIL technology has progressed with the advent of the Thermal Picture Synthesizer, TPS, which generates a thermal image using an array of resistors that are individually heated. The Applied Physics Laboratory at JHU is currently utilising an earlier generation of Nallatech's hardware in the form of a British Aerospace Scene Generator that provides real time rendered 3D images to the TPS.

Over the last two years Nallatech has been consolidating its expertise in the field of DSP implementation in FPGAs. One result of this consolidation has resulted in a new module standard that has been created to form the foundation of building future high performance data processing systems that benefit from FPGAs as a key processing element. This module standard is labeled DIME, an acronym for Dsp and Image processing Module for Enhanced fpgas.

View Entire Paper | Previous Page | White Papers Search

If you found this page useful, bookmark and share it on: