Architecture of Device I/O Drivers

Many embedded systems developers will tell you that writing a device driver consists of a lot of "bit-bashing and register-twiddling" to convince some ornery unit of hardware to submit to the control of driver software. You've got to get every one of a myriad of details right -- the bits, the sequences, the timing -- or else that chunk of hardware will just refuse to do its thing. Traditionally, the focus in writing device drivers has been at this nuts-and-bolts level. But I would like to take a somewhat different, higher-level view of device driver software.

This technical paper discusses the high-level design of driver software that is to operate hardware I/O devices that are interfaced to embedded computers. It begins with a discussion of basic driver design issues such as mutual exclusion of device access, and synchronous vs. asynchronous I/O models. Then it goes through a series of structural models for device driver design, in order of their growing complexity.

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