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An IP-based SoC Design Kit for Rapid Time-to-Market

SuperH Inc., develops and licenses 32 and 64-bit CPU cores for use in System-on-Chip (SoC) devices. SuperH has developed an innovative set of tools to reduce the 'time to market' for licensees developing SuperH based SoC devices. A description of the SoC Evaluation and Design Kit (SEDK) is provided describing its main capabilities. These include providing (i) an early software development capability, (ii) "turnkey" integration capabilities of CPU core and interconnect components, and (iii) a rapid hardware prototyping capability based on FPGAs for realizing the users own IP.

This paper presents the SoC Evaluation and Design Kit (SEDK) provided by SuperH. Further, the paper focuses on the leading edge front-end design capabilities of the SEDK. SuperH is a world leader, with a proven track record in the design and implementation of high performance RISC processors. The primary role of the SEDK is to provide SuperH customers with a modeling and hardware capability for evaluating and designing with the SuperH family of RISC cores and support peripherals for inclusion in their SoC products. Further, the kit allows the evaluation and design to be performed within short timescales.

The crucial role of achieving rapid time-to-market for company survival and commercial success has been well documented. This paper focuses on the advanced design capabilities of the SEDK for achieving this goal. These features include:

• Providing the software team with the capability of developing code early in the design process. This avoids the software bottleneck problem (which in turn increases development time) of waiting until hardware is available before starting software development.
• Providing a "turnkey" process for the integration of the core, support peripherals and interconnect of the customers design. This allows the customer to focus on their area of expertise in developing their IP. Hence a saving of effort and cost is achieved at reduced development timescales.
• Providing prototyping capability based on hardware. This is achieved with little effort and minimum timescales by realizing the core and its support peripherals on a SuperH evaluation chip and the User IP and its associated interconnect on FPGAs. This ensures User IP corrections can be rapidly evaluated.

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