This paper presents ClearSpeed's integrated Network Processor design platform that embodies many different levels of parallel processing. Designed to balance the bandwidth needs with programmability we introduce the MTAP architecture. An area and power efficient, fine-grained, scalable, multi-threaded parallel processor, designed with a 'bandwidth-centric' architecture and programmed in C.
Based on the ClearConnect bus, an SoC communication architecture with VCI compliant interfaces, a high-bandwidth system architecture including a number of hardware accelerator units is also described. An example 40 Gbps programmable and scalable classifier/forwarder is presented, embodying the concepts of the platform.
To complete the picture, a comprehensive suite of software and hardware development tools is described.
View Entire Paper | Previous Page | White Papers Search
If you found this page useful, bookmark and share it on: