IC Tools White Papers
- ATPG Pattern Compaction - the Next Wave
- Designs with Multiple Clock Domains: Avoiding Clock Skew and Reducing Pattern Count using DFTAdvisor and FastScan
- Reducing Time-to-Market Using BSDArchitect New Edition
- Solving the Challenges of Testing Small Embedded Cores and Memories Using FastScan MacroTest
- Taking Advantage of Delay Correlation Effects to Design High Speed Digital Circuits
- Challenges of 13-micron Design
- Physical Synthesis
- Low-power Synthesis Option
- Testing Large-Capacity CAM with MBISTArchitect and FastScan MacroTest
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