IC Tools White Papers
- Cost Effective Application of Phase-Shifting Mask in the Standard Cell Design Flow
- Automated Cell Optimization
- Accurate Parasitic Extraction for Subwavelength Lithography
- Systems-On-Chip for High Speed Communication Systems
- Design Planning Strategies to Improve Physical Design Flows - Floorplanning and Power Planning
- Hierarchical Design Techniques
- Power Management In Complex SoC Design
- Design Practices and Strategies for Efficient Signal Integrity Closure
- Implementing Next-Generation Radiation-Hardened ASICs
- Addressing Power Integrity Challenges for SoCs
- The Silicon Design Chain Initiative
- Silicon Design Chain collaboration extends 90nm low-power design into the mainstream
- Silicon Design Chain Extends Low-Power Design Collaboration
- SI Sign-off Verification
- Enabling Low Power Design Within an RTL-to-GDSII Implementation Flow
- RapidChip Technology Fast Custom Silicon through Platform-Based Design
- Down to the Wire - Requirements for Nanometer Design
- It's About Time: Requirements for the Functional Verification of Nanometer-scale ICs
- Agilent Technologies EDA-Instrument Connected Solutions
- Reducing ASIC Respins Using FormalPro Equivalence Checker
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