PureSpec is the most complete verification IP for validating compliance with complex interface protocols such as the PCI Express standard. PureSpec verification IP leverages the proven MMAV product architecture to provide unmatched quality, performance, and EDA tool integration. For modeling traffic generation, and the complete compliance checking, PureSpec is the most robust solution available.
Rapid growth in processor speeds and data traffic in today’s electronic system design are exposing I/O’s as an emerging bottleneck in SoC design. New protocol standards such as the PCI Express standard address the design issues, but at the same time, introduce a gap in the design verification process. The complexity of these new interface standards make it impractical for most ASIC teams to both design the interface to the standard, and create the modeling and verification environment to ensure compliance. PureSpec verification IP addresses this problem, and provides ASIC developers with a high-quality modeling and verification environment to ensure full compliance and optimal performance.
PureSpec leverages MMAV's proven C-based modeling/simulation architecture. Like MMAV, PureSpec supports all commercial Verilog, VHDL, and C-based simulations, and all popular testbench tools and languages (see full list of EDA tool integrations). In addition, to seamless testbench integration and consistent error reporting, PureSpec supports built-in and user-defined assertions which can provide call-backs to the testbench environment.
Denali's MMAV product has been used on thousands of successful ASIC designs. PureSpec is built on the same proven MMAV architecture to ensure high-quality, high-performance, and seamless EDA integrations. Proven product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec the best-in-class verification IP solution.
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