ALINT is a RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to synthesis and gate level simulation. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule viewing, editing, violation analysis, and source code cross probing.
Get Demo | Previous Page | Downloads Search
If you found this page useful, bookmark and share it on: