2/27/2006 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced immediate availability of a 90-nanometer reference flow that addresses power-management and design-yield issues. The new flow is part of an ongoing collaboration with IBM and Chartered Semiconductor Manufacturing. The companies developed this design reference flow for the 90-nm low-power process technology on the IBM-Chartered Common Platform and to provide innovative solutions to accelerate time to market for system-on-chip (SoC) designs.
The new RTL-to-GDSII reference flow is based on the Cadence® Encounter® digital IC design platform and enables higher productivity and improved quality of silicon (QoS). The reference flow addresses critical low-power design challenges, from chip prototyping through power, timing and area optimization. The Cadence SoC Encounter GXL RTL-to-GDSII system enables timing-aware leakage power and dynamic power optimization, using power techniques such as multi-supply voltages, multiple-Vt optimization, and clock gating. This optimization helps designers improve timing closure and reduce device area, while lowering power consumption without compromising performance.
"IBM and Chartered continue to drive the Common Platform for 90-nanometer designs and beyond," said Steve Longoria, vice president of Semiconductor Common Platform for IBM Systems & Technology Group. "We worked closely with Cadence to enable a low-power, yield-aware design methodology to reduce design and manufacturing risk. This next phase in the design chain collaboration with Cadence expands our open ecosystem based on collaborative innovation."
The flow addresses nanometer defect yield issues with yield analysis and optimization capabilities embedded in critical implementation stages such as physical synthesis and routing. For yield analysis, full-chip or block-level defect yield losses are assessed based on factors such as critical area and cell yields. An innovative yield prototyping capability enables designers to choose full-chip floorplanning strategies with visibility of yield considerations before committing to a physical architecture for the chip, allowing them informed design choices to speed yield ramp. For nanometer designs, wiring has growing impact on final chip yield. This is addressed by optimizing double-via insertion, wire spacing and other factors concurrently during routing, instead of a separate post-processing step.
"Our collaboration with the leaders in the Common Platform-IBM and Chartered-aligns industry breadth and depth to address the complexity of design facing our customers today," said Jan Willis, senior vice president, Industry Alliances, at Cadence. "This 90-nanometer low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform."
The flow incorporates several innovative Cadence technologies, including Encounter RTL Compiler global synthesis, the SoC Encounter GXL system, Encounter Test, Encounter Conformal Low-Power verification, and Cadence QRC extraction. Other Cadence components includeVoltageStorm® Dynamic Gate power rail analysis, and CeltIC® Nanometer Delay Calculator (NDC), using the highly accurate effective current source delay model (ECSM) to enable designers to reduce time-to-volume for low-power consumer applications. ARM® Metro(tm) low-power products, part of its family of Artisan® physical IP, are used for the flow development.
"Support from our EDA partners like Cadence allows us to provide our customers with solutions that accelerate their path to silicon while offering them the flexibility benefits and sourcing options of our collaborative strategy with IBM," said Kevin Meyer, vice president of worldwide marketing and platform alliances at Chartered. "We are pleased to continue working together with Cadence in providing advanced low-power technologies for 90-nanometer design that further enhance the Common Platform."
Cadence, Chartered, IBM and Samsung are working on a reference flow targeted at the Common Platform's 65nm LP process.
This 90-nanometer low-power, yield-aware design reference flow is available immediately by sending an email request. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.
On Wednesday, April 26, 2006, at 10 am (PST), Cadence, Chartered and IBM will hold a free Webinar on advanced low-power design techniques used in this reference flow. For more information about registering for this event, please send email.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, the Cadence logo, Encounter, CeltIC, and VoltageStorm are registered trademarks of Cadence Design Systems, Inc.
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