2/14/2006 - Cadence Design Systems, Inc. (NASDAQ: CDNS) introduced the Cadence® Virtuoso® Resolution Enhancement Technology (RET) Suite. The Virtuoso RET Suite integrates lithography awareness directly into the Cadence Virtuoso custom design platform, the leading design environment for custom ICs. With the Virtuoso RET Suite, designers targeting sub-90-nanometre manufacturing technologies are now able to create layout designs that are less sensitive to critical yield-degrading lithography issues, and which are de-sensitized to common lithography-process variations.
The Virtuoso RET Suite allows designers to analyze and optimize designs for both performance and yield by examining precisely how target layout structures will appear in silicon. This is done by precisely modeling the distortions that are inherent in today's sub-wavelength lithography. The suite includes interactive model-based simulation of layout designs, batch and interactive lithography rule checking, lithography-yield analysis and optimization, and trial-based optical-proximity-correction (OPC) capabilities utilizing critical lithographic parameters, including illumination mode, exposure and focus.
"We are pleased to adopt the Virtuoso RET Suite for use on our advanced DRAM memory processes," stated Mr. Takao Adachi, Officer, CTO, Technology & Development Office at Elpida Memory, Inc. "As a leading memory manufacturer, optimizing our designs for lithography accuracy addresses critical concerns by improving manufacturing precision and yield. We look forward to Cadence continuing to develop and provide solutions that enable lithography-aware designs to avoid costly and time-consuming re-spins."
The Virtuoso RET Suite is based on technology developed through Cadence's previously announced developmental agreement with ASML, the world's leading provider of lithography systems for the semiconductor industry. With its tight integration into the Virtuoso environment, the Virtuoso RET Suite offers the same, familiar and intuitive user interface and use model that most layout designers routinely use today, thereby promoting easy adoption.
Dr. Marc Levitt, vice president for Design for Manufacturing (DFM) at Cadence, said, "The Virtuoso RET Suite graphically illustrates our strategy of putting the 'Design' back into 'DFM.' Traditional post-processing DFM solutions have proven insufficient to address the demanding requirements of the most advanced semiconductor lithography and manufacturing. Creating high-yield, high-performance designs requires that layout designers be aware of manufacturing effects. The Virtuoso RET Suite directly addresses this need by allowing layout designers to see exactly what the resulting silicon will look like when manufacturing effects are considered."
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry.
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