2/8/2006 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® X Architecture design solution has won the International Engineering Consortium (IEC) DesignVision award for ASIC and IC Design Tools at DesignCon 2006. The Cadence X Architecture design solution is the industry’s first IC physical implementation system enabling designers to implement chips using the innovative X Architecture.
The X Architecture represents a new way of orienting a chip’s microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle "Manhattan" routes. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly reduced wirelength and fewer vias (the connectors between wiring layers).
"We are honoured that the IEC selected the Cadence X Architecture design solution as the winning entry in this very competitive category," said Kalyan Thumaty, vice president and general manager of X Architecture at Cadence. "The Cadence X Architecture design solution provides the industry with a revolutionary new way to optimize IC design cost, performance and power consumption for today’s challenging market needs, making it an ideal solution for consumer, wireless and graphics market segments. The DesignVision award is further validation of our commitment to innovation and focus on end-user needs."
The Cadence X Architecture design solution enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow. While leveraging Cadence’s industry-proven Manhattan implementation expertise, the solution draws on innovations in placement, routing, infrastructure and extraction technologies.
ATI Technologies Inc. and Toshiba Corporation have successfully leveraged the Cadence X Architecture design solution and enjoyed its compelling benefits.
ATI implemented a high-performance, high-volume PCI-Express graphics processor using the Cadence X Architecture design solution and manufactured it using the TSMC 0.11-micron process. This enabled them to eliminate one metal layer from the design, reducing the device’s die cost.
Toshiba's chip, TC90400XBG, designed for integration in digital-media and home-entertainment applications, was fabricated using 130-nanometer process technology and is approximately 11 percent faster in speed and 10 percent smaller in random logic area compared to equivalent Toshiba products with the conventional "Manhattan" design.
Foundry leaders TSMC and UMC provide production support for the manufacture of chips implemented using the X Architecture. TSMC is production-ready for 0.13-micron, 0.11-micron and 90nm process nodes. UMC accepts X Architecture designs for fabrication at 130 and 90nm process nodes.
About the DesignVision Awards
The DesignVision Awards program recognizes technologies, applications, products, and services judged to be the most unique and beneficial to the industry. The DesignVision Awards also honour corporations and individuals for innovative contributions and developments that have proven important to society.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry.
Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.
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