1/10/2006 - EVE (Emulation and Verification Engineering) announced availability of a catalog of peripheral intellectual property (IP) components for its winning ZeBu emulation platform to address wireless, graphics/video/multimedia, networking and embedded processor markets.
Components are organized in three families –– synthesizable memory models, transactors and hardware bridges –– and allow EVE to offer vertical solutions of its ZeBu ("zero bugs").
"Unlike classical verification IPs, our components are designed for extremely high performance tuned to our ZeBu platform," says Lauro Rizzatti, General Manager of EVE-USA and Vice President of Worldwide Marketing. "Our investment in this high-quality catalog of industry-standard components is paying off handsomely. It has given ZeBu-based design teams an accelerated path to market."
Earlier last year, EVE organized a task force to create peripherals and protocol IP testbench components to work with ZeBu. These components, which mimic specific protocols, are used to develop and verify electronic devices, such as mobile phones, personal digital assistants (PDAs), digital television/high-definition television (DTV/HDTV), set-top boxes, personal computers, storage and peripheral devices.
Verification productivity of system-on-chip (SoC) and application-specific integrated circuit (ASIC) designs is boosted by connecting the design mapped onto ZeBu to a set of peripherals and run at several MHz speed on very large designs at the transaction level and/or in-circuit emulation.
They create an environment that merges real and/or virtual peripheral and protocol IP to enable system-level verification. The result is that corner-case bugs in hardware and in embedded software such as drivers and complete applications can be quickly pinpointed and corrected.
Compliance and interoperability testing can be efficiently accomplished, giving designers the confidence that their designs meet delivery schedules.
Currently, EVE’s vertical solution components include a complete family of synthesizable memory models, a set of transactors to support popular protocols, and a couple of hardware bridges. These components can also be combined together to provide more flexibility and performance. More components will be announced as they are available.
ZeBu memory models are an accurate replica of real memories, and include a comprehensive set of SDR, DDR, DDR2, and DIMM DRAM synthesizable models compatible with Micron or Samsung memory chips as well as NAND flash memory models of different sizes. They support memory upload/download and read/write of each and every cell at run-time for interactive design debugging.
ZeBu transactors interface a testbench written in C/C++/SystemC/SystemVerilog at high-level of abstraction to a DUT mapped in ZeBu and mimic a specific protocol. Designed to privilege very fast execution speed they are based on the ZeBu efficient API and are mapped onto the Reconfigurable Test bench (RTB), a proprietary and patented technology devised by EVE. Currently, the family includes protocols such as PCI Express with 1x/2x/4x/8x lanes, Ethernet 10/100/1G, Ethernet controller, LCD, JTAG, UART, keypad, keyboard and mouse. A memory transactor extends the design memory to the PC RAM and supports MHz access.
For compliance testing of standard protocols, the ZeBu hardware bridges interface a physical peripheral to a very complex DUT mapped onto ZeBu executing at a fraction of the real speed. Currently, the bridges include PCI/PCI-X and PCI Express with 1x/2x/4x lanes protocols. For smaller designs (< 3 M ASIC gates) or IPs, the new ZeBu-UF platform also supports most interfaces (DRAM, Video, USB…) at real speed.
Pricing and Availability
The ZeBu Vertical Solution Catalog is shipping now at a starting price of $5,000 per component for one-year term-based license.
About Emulation and Verification Engineering
EVE (Emulation and Verification Engineering) offers the fastest verification and most cycles per dollar by combining the best aspects of traditional emulation and rapid prototyping systems into a single, unified environment for both ASIC and SoC debugging and embedded software validation. Its corporate headquarters is located in Palaiseau, France. Its headquarters in the United States is San Jose, Calif. Email: firstname.lastname@example.org
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