Fujitsu to Ship New Structured ASIC Built Using Cadence Encounter

8/2/2005 - Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) and Fujitsu Microelectronics America, Inc. (FMA) announced that FMA will ship initial production volumes of a new, highly complex, structured ASIC using Cadence® Encounter® digital IC implementation in August. Encounter, which was originally developed for standard ASICs, provided rapid timing closure with signal integrity for optimal quality-of-silicon (QoS) in the implementation phase of the design flow for FMA's AccelArrayTM family of structured ASICs.

"We chose the Encounter platform as the netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility in implementing standard ASIC and structured ASIC designs," said Noboru Yokota, senior director of engineering at FMA. "This very complicated design, which FMA completed with AccelArray Giga Frame, implements about 1.4 million instances of cell."

The design incorporates 3.5 million logic gates, 119 instances of 2RW SRAM (40bx512w), 33 instances of register file (40bx32w) and 12-channel, 3.125G SERDES for high-end servers developed for consumer applications. The design was completed with low, non-recurring costs by using AccelArray Giga Frame.

"We are very happy with the success of our work with important customers such as Fujitsu," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "This is another example of the Cadence Encounter platform's rapid route to complex, high-performance SoC implementation."

The Fujitsu AccelArray Giga platform addresses the specific needs of mid-volume vertical markets that require the performance of cell-based ASICs. These platforms leverage Fujitsu's decades of ASIC design and system-level expertise in the networking, storage networking, next-generation consumer electronics and imaging markets. Giga platforms reduce back-end physical design time such as DFT insertion, power mesh, clock tree synthesis and simultaneous switching output (SSO) analysis, all of which can consume a considerable amount of time. The Giga platform offers up to 75Gbps of full-duplex SERDES aggregated bandwidth by incorporating pre-diffused universal G-PHY macro cells.

SoC Encounter GPS combines RTL synthesis, silicon virtual prototyping, and full-chip implementation into a single system. It enables engineers to synthesize to a flat virtual prototype implementation-including full-chip, routed wires-right at the beginning of the design cycle. With SoC Encounter GPS, engineers have an early, accurate view of whether the design will meet its targets and be physically realizable. Designers can then choose either to complete the final implementation or to revisit the RTL design phase.

About Fujitsu Microelectronics America
Fujitsu Microelectronics America, Inc. (FMA) leads the industry in innovation. FMA provides high-quality, reliable semiconductor products and services for the networking, communications, automotive, security and other markets throughout North and South America. For product information, visit the company web site at or please address e-mail to

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

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