7/29/2005 - AccelChip Inc., the industry’s only provider of automated flows from MATLAB® algorithms to silicon, has become the first company to provide a family of fixed-point linear algebra intellectual property (IP) cores for Xilinx FPGA devices.
AccelChip’s matrix inverse and factorization cores are being offered through Xilinx’s third-party Alliance Program. The Alliance Program, which includes independent core developers, is designed to produce a broad selection of industry-standard solutions dedicated for use in Xilinx programmable logic.
The AccelChip cores, the first of their kind, directly implement linear algebra-based matrix operations used in applications such as sensor array processing, beamforming, global positioning, radar/sonar, Kalman filtering, and wireless communication applications. Targeted at hardware designers and system engineers who implement these applications in silicon, AccelCoreTM DSP IP delivers synthesizable, VHDL/Verilog linear algebra cores that are highly optimized in terms of speed, power, and size.
“Our DSP customers use a combination of both HDL and Xilinx System Generator for DSP Design,” said David Squires, Director of DSP Marketing in the DSP Division at Xilinx. “The addition of AccelCore into the Xilinx Alliance Program has the potential to save months of development time, regardless of design entry methodology with proven linear algebra-based matrix cores for advanced wireless and signal processing applications.”
“IP is fast becoming an essential element of DSP design, thanks to its ingrained reusability and ever-increasing quality,” said Dr. Tom Cesear, chief scientist at AccelChip Inc. “The Xilinx Alliance Program evaluates cores for listing in the program by certifying that they have been fully synthesized, placed and routed on Xilinx FPGAs. AccelChip is proud to work with Xilinx to now offer AccelCore DSP IP in the FPGA industry’s largest 3rd-party IP program.”
The initial offering of AccelCore DSP IP available through the Xilinx Alliance Program includes QR matrix factorization and inverse, Cholesky matrix factorization and inversion, and singular value decomposition (SVD).
Simulation models for AccelCore DSP IP are available from AccelChip to test and simulate their functionality and throughput in customer designs. This allows the user to get a true representation of how the cores will behave in their specific design. Each AccelCore is available separately under the standardized Xilinx SignOnce IP License agreement.
About the SignOnce IP License
Xilinx, the leading provider of programmable logic devices, and over 55 third-party IP providers have agreed to offer customers a single set of common IP licensing terms, called the SignOnce IP License, for acquiring FPGA-based IP cores. The result is a first for the IP industry - a single set of licensing terms, giving customers access to IP cores from multiple vendors for use in Xilinx programmable logic. For more information on this program, go to www.xilinx.com/ipcenter/signonce.htm.
AccelChip Inc. is the industry’s only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip’s proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com.
AccelChip, AccelWare, and AccelView are registered trademarks of AccelChip Inc. AccelCore is a trademark of AccelChip Inc.
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