6/14/2005 - Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) announced that Agere Systems chose the Palladium® II accelerator/emulator system after using the original Cadence® Palladium system to verify and launch its TrueAdvantageTM converged access solutions. The increased capacity of Palladium II will significantly reduce the overall functional verification process of Agere’s most complex chip designs.
Agere cited the Palladium II system’s high-performing multi-user capabilities, increased run-time performance, and strong debug capabilities. The overall result will enable Agere to begin the verification of the hardware and software up to three months earlier in the design process—directly addressing intense time-to-market pressures.
According to Agere, the entire verification environment for the TrueAdvantage converged access solutions was up and running within two weeks. This included third-party IP, the operating system and external debuggers, and connections to external networking-test sets such as Bit-gate and Adtech.
“The Palladium II system offers attractive system-level verification process capabilities with swift compile time,” said Craig Garen, director of telecom engineering with Agere Systems. “We also found the multi-user approach, enhanced debug capabilities, and proven external test-equipment interfaces to be extremely valuable.”
Agere also leveraged the Palladium system to accelerate pre-silicon development and prove-in of multiple layers of software, including microcode, firmware, drivers and application programming interfaces. The ability to run the chip and software with real-world data traffic significantly improved the quality of the initial software release— allowing delivery of software with early samples of the chip.
“Agere’s initial success with the Palladium system is exactly the reason they chose to continue to work closely with Cadence on the Palladium II,” said Christopher Tice, senior vice president and general manager, Verification Acceleration, Cadence. “Cadence is confident the Palladium II system will generate significant time savings for Agere, allowing the company to meet or exceed its product delivery goals.”
First Silicon, First Software
An integral component of the IncisiveTM verification platform, Palladium II delivers hardware acceleration and in-circuit emulation in a single system scalable from IP core development to full system-on-chip designs, helping move customers quickly to first silicon and first software. The system provides a flexible debug and advanced verification environment that includes transaction and assertion-based acceleration solutions. Additionally, with the Palladium II customers have the ability to leverage Cadence’s turnkey vertical market solutions such as the multi-Ethernet SpeedBridge®.
Cadence recently introduced Palladium II, which is one-third the size and twice the speed of the original Palladium system.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, the Cadence logo, and Palladium are registered trademarks of Cadence Design Systems in the United States and other countries. Incisive and SpeedBridge are trademarks of Cadence Design Systems.
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