5/31/2005 - Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the new products and solutions it will be displaying at the 2005 Design Automation Conference (DAC) at booth #1023 in Anaheim, California, June 13-17.
System Level Platform
Aldec will be presenting its new generation of system level design capabilities and several advanced features for private viewing during the show. Anticipated release of the solution is scheduled for Q3 of 2005. Features include:
Mixed Digital/Analog Simulation
Aldec will be showing a private demonstration of an all new system-level mixed analog/digital simulation solution. The solution is based on Aldec’s industry-proven VHDL, Verilog and SystemVerilog mixed-language simulation technology and the Turbo Spice simulator for new generation system-on-chip designs.
C/C++ Testbench Automation
Aldec will present a complete, automated environment for writing and executing C/C++ testbenches for verification. All necessary libraries, compilers and debugging tools are included at no extra cost with standard versions of Aldec verification products. Also included are complete C++ programming capabilities, testbench-specific libraries for efficiently creating HDL testbenches, and standards-based reuse of the code. SystemC testbenches are typically 10 to100 times faster than VHDL and Verilog testbenches due to the higher level of abstraction in SystemC.
System Level Language
A key element of system-level design and verification is the ability to describe the system in a higher, more efficient language structure. These higher-level languages include SystemC, C/C++, SystemVerilog and assertion-based verification. Aldec will provide a demonstration of the advantages and strategies for using each of these system-level design languages using both Active-HDL and Riviera.
Many DSP designers use MATLAB to create a model of the signal processing application before it is implemented and MATLAB simulations with Simulink are often used to test the DSP behavior. Aldec will provide a demonstration using Active-HDL and Riviera in conjunction with MATLAB and Simulink for co-simulation and testing of HDL and DSP designs.
Register for a Demonstration
To schedule some time to view Aldec’s solutions, please visit register.aldec.com/Registration/DAC/DAC2005.aspx
Latest ESNUG Report Says “Aldec Active-HDL 6.3 Crushes Mentor ModelSim”
To read what customers have to say about Active HDL 6.3 versus Mentor’s ModelSim see the report on DeepChip at www.deepchip.com/items/0445-07.html.
Aldec, Inc., a 21-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at www.aldec.com.
Active-HDL, Riviera and Incremental Prototyping Technology are trademarks of Aldec, Inc.
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