Lattice's TransFR Technology Enables Transparent FPGA Reconfiguration

5/27/2005 - Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate, no charge availability of its ispVM® programming software that supports its breakthrough Transparent Field Reconfiguration (TransFRTM or TFR) capability. Lattice's TransFR technology allows designers to reconfigure LatticeXPTM non-volatile FPGAs in the field without interrupting system operation. LatticeXP FPGAs uniquely employ on-chip Flash plus SRAM technology to give an ideal FPGA technology combined with an optimized general-purpose FPGA architecture.

"Field FPGA reconfiguration, driven by bug fixes, changing standards, equipment upgrades and addition of services, continues to grow rapidly in importance," said Stan Kopec, Lattice vice president of corporate marketing. "At the same time, many system vendors would like to reconfigure product features in the field while maintaining '5 nines'--99.999% -- system availability. For the first time, Lattice's unique TFR capability, enabled by our LatticeXP silicon and ispVM programming tool, makes transparent field reconfiguration a reality without appreciable system downtime," Kopec concluded.

ispVM Programming Tools Automate TFR Implementation
Lattice's ispVM software is a Windows-based tool set that facilitates the programming of Lattice devices. The ispVM Embedded tool generates C code that, when compiled for and executed on a wide range of embedded processors, enables the programming of Lattice devices. Field logic reconfiguration can be achieved in two stages using the ispVM software. First, a "Background" programming command loads new data into the Flash memory of the LatticeXP device transparently without halting FPGA operation. Second, at an appropriate time, device operation can be briefly suspended while an "XFlash TransFR" command updates the SRAM from the Flash block in approximately 1 millisecond. This update can occur while holding the I/Os in user-defined states to avoid disturbing the surrounding system's operation. The ispVM software can either issue the commands directly via a programming cable (serial or USB) during prototyping, or generate an industry-standard Serial Vector Format (SVF) file for reconfiguration in the field.

The latest version of the ispVM tool, 15.2, is available for download free of charge from the Lattice web site at:

The TransFR Flow
Until now, field logic reconfiguration has been a difficult and time-consuming chore. TFR simplifies the task by making this complexity transparent to the user. The TFR sequence requires only four simple steps:

  1. The on-chip Flash memory of the LatticeXP device is programmed while the device operates out of SRAM.
  2. The I/O states are locked at their current or a fixed value (high, low, or high-Z) by issuing commands through the JTAG interface and device operation is effectively suspended.
  3. A command is issued through the JTAG interface to update the SRAM configuration from Flash. This typically takes less than 1mS.
  4. The on-chip logic resumes operation and is functional and responding to inputs, allowing it to be placed into a known state. A command is then issued through the JTAG interface to release the I/O.

Steps 2 through 4 are implemented with a single ispVM command.

About LatticeXP FPGAs
Non-volatile LatticeXP FPGAs deliver the benefits of instant-on operation, excellent security and a single-chip implementation, and provide cost-effective alternatives to traditional SRAM-based FPGAs and their associated boot memories. The ispXPTM technology used in the LatticeXP devices combines SRAM and non-volatile Flash memory to deliver an FPGA that is both non-volatile and infinitely reconfigurable. The SRAM-based memory cells control the operation of the device logic and are loaded from the on-chip Flash memory in less than 1mS at power-up -- providing instant-on capability -- or on user command. Unlike SRAM-based FPGAs, the LatticeXP device does not require an external boot memory and so provides a single-chip solution with the associated benefits of reduced board area and simplified system manufacture. The absence of an external boot device also eliminates the need for an external bit-stream at boot up and the possibility of bitstream snooping, a major security concern with SRAM FPGAs. Security features prohibit bit-stream readback from the SRAM and Flash sections of the devices to further enhance security.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC®) and Programmable Digital Interconnect Devices (ispGDX®). Lattice also offers industry leading SERDES products.

Lattice is "Bringing the Best Together" with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and "single chip solution" space savings. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispGDX, ispPAC, ispVM, ispXP, LatticeXP, TransFR and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

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