EVE Adds Capabilities to ZeBu Hardware-Assisted Verification Platform

5/18/2005 - Emulation and Verification Engineering (EVE) announced new capabilities to its ZeBu hardware-assisted verification platform that include a transaction-level interface to Native Testbench (NTB) in Synopsys, Inc.’s VCS® comprehensive RTL verification solution, support for SystemVerilog assertions and automated design clustering software for easy and fast set up.

These new capabilities within ZeBu –– or Zero Bugs –– will be demonstrated at the 42nd Design Automation Conference (DAC) in EVE’s booth number 1020 fromJune 13-16, at the Anaheim Convention Center in Anaheim, California.

The ZeBu platform now offers a high-performance, transaction-level interface to Synopsys’ VCS solution.The interface enables advanced testbenches running in VCS NTB to drive and monitor designs running on ZeBu at MHz speed.

The interface can utilize a Synopsys Reference Verification Methodology (RVM) transaction-level channel class interface, enabling the upper layers of an RVM-based testbench to run in VCS, while lower layers of the testbench and the design under test (DUT) can be simulated in either the VCS solution or the ZeBu platform.

This approach enables customers of the VCS solution to apply native technologies, such as constrained-random stimulus generation and comprehensive functional coverage, to designs running on ZeBu.

In addition, concurrent and temporal synthesizable SystemVerilog assertions are fully supported by ZeBu to provide coverage feedback or to control the emulation execution.They can be used in any mode of operation, from co-emulation with a software testbench to In-Circuit-Emulation.

A new 64-bit clustering software eases the traditionally complex task of mapping an ASIC or SoC design into an array of FPGA devices.The new capability automates the entire mapping process, and includes the breaking of a design into multiple blocks, the handling of complex clock trees and large busses, and the routing of high connectivity data path.In the current implementation, clustering supports up to 64 of the largest FPGAs.Based on Xilinx Virtex-II 8000 FPGAs, the scalable ZeBu platform boasts the industry’s largest capacity FPGA prototyping system of up to 50 millions ASIC gates.

“Our ZeBu platform is the only verification solution on the market to address hardware/software integration and embedded software validation at more than five MHz on designs exceeding 10 million ASIC gates,” says Lauro Rizzatti, Worldwide Marketing Vice President and EVE-USA General Manager. “ZeBu does not require specialized prototyping technology experts to map a complex design.”

Priced at pennies per gate, ZeBu sets the standard for most execution cycles per dollar.It targets hardware debugging, hardware and software integration, and embedded software validation prior to silicon.

Pricing and Availability
The new clustering capability is included in the ZeBu compiler at no extra charge.The transaction-level interface to Synopsys’ VCS solution and SystemVerilog assertions support are options priced at $20,000 each.

The Synopsys VCS solution is available from Synopsys separately.

About Emulation and Verification Engineering
Emulation and Verification Engineering (EVE) pioneers a new approach to hardware-assisted verification that combines the best aspects of traditional emulation and rapid prototyping systems into a single, unified environment for both ASIC/SoC debugging and embedded software validation. Its corporate headquarters is located in Palaiseau, France. Its headquarters in the United States is San Jose, Calif. Email:info@eve-team.com Website: www.eve-team.com

VCS is a registeredtrademark of Synopsys, Inc.

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: