3/8/2005 - Cadence announced customer ratification of its low-power enhancements to Cadence Encounter CeltIC NDC (Nanometer Delay Calculator), a leading industry solution for signal integrity (SI) signoff.
Leveraging the Cadence effective current source model (ECSM), CeltIC NDC supports signoff analysis of low-power designs that include multiple supply voltages and multi-threshold cells. This includes accurately modeling the combined impact of crosstalk and supply voltage (IR) drop on timing and noise immunity by reading IR drop information from Cadence VoltageStorm power analysis.
"At nanometer geometries, IR drop effects are getting increasingly severe," said Noam Benayahu, director of VLSI of Metalink. "CeltIC NDC utilising ECSM enabled us to pinpoint design regions that had potential IR drop-induced timing problems. CeltIC NDC is now an essential step in our signoff analysis since it can help avoid costly silicon failures."
"It is essential that our designs meet timing while accounting for signal integrity," said Jamshed Qamar, vice president, engineering at Oki Semiconductor. "CeltIC NDC plugged directly into out timing signoff flow and delivered very good accuracy with respect to SPICE when accounting for both IR drop and crosstalk effects. We found its ability to perform on-the-fly path simulation a very easy and productive way to further validate our critical paths."
"Timing closure is key to all ARM Partners and the effects of SI are increasing as the silicon geometries get smaller and the demand for lower operating voltages prevails. ARM has been supporting CeltIC tools for the last three years to ensure that our mutual customers get accurate SI information in a familiar format," said Mike Inglis, executive vice president of Marketing for ARM. "We have seamlessly upgraded to CeltIC NDC so that we can continue to supply our mutual customers with latest formats."
CeltIC NDC also includes a breakthrough technology called path-based alignment (PBA) that significantly reduces SI delay pessimism, often by a few hundred picoseconds or more, resulting in much faster SI closure. Other capabilities include reporting of potential doubling clocking failures, SPICE deck generation of critical paths (including SI) and a 30 percent reduction in memory usage. Significant ease-of-use improvements have also been made to the commands, reporting and diagnostic capabilities.
"Low-power designs suffer from an increased sensitivity to signal integrity effects due to the combined usage of multiple supply voltages and multi-Vt cells," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "CeltIC NDC, a core technology of the Encounter platform, has been enhanced both to address low-power design challenges and to enable faster SI closure of leading-edge nanometer designs."
Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com.
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