3/4/2005 - Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of its Rake Receiver reference design, targeted at base stations in wireless telecom applications. A Rake Receiver is used to counter the effects of RF multipath fading due to atmospheric absorption, ionospheric reflection and refraction, and reflection from terrestrial objects such as mountains and buildings. The technique uses several sub-receivers, each delayed slightly, in order to tune in the individual multipath components and then combine them to optimize the signal reception. The reference design uses the new LatticeECPTM (EConomy Plus) FPGAs that combine an optimized FPGA fabric with high-speed, dedicated DSP blocks on-chip.
"LatticeECP-DSPTM FPGAs are ideal for applications in which cost-effective DSP functionality is needed," said Stan Kopec, Lattice vice president of corporate marketing. "Our new Rake Receiver reference design is specifically designed to take advantage of the device family's embedded DSP support, delivering high-speed channel correction in a low-cost FPGA fabric. This W-CDMA solution is another example of Lattice 'Bringing the Best Together' with unique silicon plus application expertise that gets our customers to market fast," Kopec added.
Lattice ispLever® v4.2 design software supports the ECP family for design entry, simulation, and place and route. In addition, the reference design includes a model of the Rake Receiver generated using The MathWorks Matlab®. The model supports data generation and simulation capabilities in the popular Matlab environment.
Rake Receiver Reference Design Features
The reference design has the following features (one instance of the rake engine):
Availability and Pricing
The Rake Receiver reference design is available now for qualified Lattice customers. A white paper and user guide for the reference design can be found on the Lattice website at http://www.latticesemi.com/products/devtools/ip/refdesigns. Source code for the design may be obtained free of charge through local Lattice sales offices.
About the Lattice ECP FPGA Family
The new LatticeECP-DSP products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace.
About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC‚), and Programmable Digital Interconnect Devices (ispGDX‚). Lattice also offers industry leading SERDES products. Lattice is "Bringing the Best Together" with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, consumer, industrial and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit www.latticesemi.com
Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispGDX, ispLever, LatticeECP, LatticeECP-DSP, ispPAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
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