3/2/2005 - Prosilog SA, a leading provider of innovative solutions for SoC design and verification, announces the integration of Yogitech’s OCP eVC, in Magillem, its platform based design environment. As any other IP block within Magillem, the eVC is imported, configured and connected to the DUT (Design Under Test). Yogitech’s eVC is registered in the Magillem Verification IPs list, and the user can select and parameterize the OCP interfaces required for the test (OCP 2.0 or 1.0, master or slave).
Then Magillem provides an assistant, compatible with the eRM (e Reuse Methodology), which generates the e configuration code. It allows to easily set all the parameters of the verification agents (master, slave or monitor) for configuration, monitoring and BFM behavior; the mapping of the e variables on the HDL signals can also be changed.
Finally, Magillem generates the platform interconnection code (in VHDL, Verilog or SystemC), and the bus matrix, bridges, protocol wrappers or multi abstraction levels adapters, provided by Prosilog both as synthesizable or simulable models. All this generated code can be used by any HDL compiler to simulate the DUT.
"This integration which has been developed in collaboration with our technical team, allows to save time during the critical phase which consists in designing and setting up the verification platform," says Silvano Motto, CEO of Yogitech. "The generation of the whole e code which is mandatory to configure our OCP eVC is now automated by Magillem."
"OCP eVC is the only complete and reliable solution available on the market to verify SoC designs incorporating the OCP interface, successfully adopted by customers worldwide," continues Mr Motto. "We have a strong commitment to reinforce the thriving infrastructure surrounding OCP and the partnership with Prosilog is surely moving in this direction."
"Thanks to the collaboration with Yogitech, we demonstrate the capability to use Magillem as a verification cockpit to drive the Verisity verification tools suite," says Emmanuel Vaumorin, Technical Marketing Manager for Prosilog. "Any eVC which follows the eRM methodology can be integrated in Magillem in the same way in order to significantly reduce the verification cycle time."
"We are pleased to see that Prosilog, through Magillem, provides to the SpeXsim users, an innovative solution which automates part of the e verification code generation," says Michel Telera, Area Director for Southern Europe for Verisity. "One of Verisity’s goal is to encourage new partnerships between the different actors of the verification market, such as eVCs providers like Yogitech and tools providers like Prosilog."
About Prosilog SA
Prosilog SA is developing innovative System Level Design and RTL tools, as well as soft IP cores, which help SoC designers reduce the cycle time of their product design.
Magillem, the Prosilog’s response for platform based design, handles system descriptions both at RTL and transactional levels. With the SPIRIT editor, people can import and instantiate IPs according to the SPIRIT 1.0 specification.
The graphical front-end allows the easy integration of different IP blocks, the automatic generation of the interconnection between IPs as well as the insertion of verification modules.
The IP Creator module enables the fast generation of an OCP or VCI wrapper, making it easy to create a common interface for any IPs portfolio. Once the design is built, the netlist is exported to the different VHDL, Verilog or SystemC RTL/TLM languages, and packaged in the SPIRIT format.
For information visit: www.prosilog.com
YOGITECH SPA is a semiconductor company with a proven experience in System-on-Chip design&verification and in fault-tolerant integrated circuits. Founded in 2000, YOGITECH is leveraging a unique expertise in Specman Elite. Sponsor Member of OCP-IP, YOGITECH is tier 1 Partner in Europe of Verisity and ARM Technology Access Partner.
YOGITECH offers a catalogue of eRM e Verification Components (eVCs), to shorten time-to-production of IPs and systems based on standard protocols, like ATAPI, CAN, LIN and OCP, successfully adopted by major semiconductor companies in Europe, US and Asia.
Verisity Ltd. (Nasdaq: VRST) is the leading supplier of process automation solutions for the functional verification market. The Company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing, and consumer electronics global markets. Verisity's VPA solutions enable projects to move from executable verification plans to module, unit, and chip/system level 'total coverage' and verification closure, while maximizing productivity, product quality, and predictability of schedules.
The Company's strong market presence is driven by its proven technology, methodology and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. Verisity is a global organization with offices throughout Asia, Europe, and North America. Verisity's principal executive offices are located in Mountain View, California, with its principal research and development offices located in Rosh Ha'ain, Israel. For more information, visit www.verisity.com.
Magillem® is a registered trademark of Prosilog SA.
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