S3 Succeeds with Cadence Encounter Digital IC Design Platform

2/25/2005 - Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) announced that the Cadence® EncounterTM digital IC design platform has helped Silicon & Software Systems (S3), a leading System IC design company, deliver multiple 90 nanometer designs over the past 18 months. The designs ranged in complexity and size from 1 million to 4 million gates, with performances in excess of 600MHz.

“S3 has made a substantial investment in developing flows and expertise to minimize the risks for our customers in 90-nanometer system IC design, with a focus on performance and high quality of results,” said Dermot Barry, general manager of the System IC Business Unit at S3. “The SoC Encounter digital IC design tool provides the early feasibility testing and budgeting we require for our complex designs, and a rapid timing and SI (signal integrity) closure with the CeltICTM and NanoRouteTM.”

S3’s successful 90 nanometer results are on par with more mature process technologies. With 15 designs started at 90 nanometers to date, and two 65-nanometer designs underway, S3 is at the leading edge of system IC design in an industry now seeing volume ramp-up at the 90-nanometer technology node.

Recent S3 deliveries include a 4-million-gate system on a chip in a nine metal layer, 90-nanometer process with clock speeds in excess of 600MHz, and a 1-million-gate 90-nanometer CMOS ARM11 subsystem with multiple power domains.

“S3 has clearly demonstrated leadership at the 90-nanometer technology node, and is further extending its leadership with multiple, complex 65-nanometer designs currently underway,” said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. “We applaud the engineering team at S3 on its success and are proud that it has chosen Encounter as the standard for leading-edge implementation. Once again, Encounter is recognized as essential technology by an important customer.”

The Encounter platform covers the spectrum of nanometer design technology from prototyping and partitioning to final timing and SI closure on the most complex designs. Encounter’s partitioning and prototyping methodology allows designers to quickly achieve optimal timing budgets and floorplanning in the early phases of the project. Its crosstalk prevention features, coupled with NanoRouteTM SI aware routing provide a fast path to GDSII and final design closure at 90 nanometers.

About Cadence
Cadence is the world’s largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics-based products. With approximately 4,900 employees and 2004 revenues of approximately $1.2 billion, Cadence has sales offices, design centres, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks and Encounter, SoC Encounter and NanoRoute are trademarks of Cadence Design Systems, Inc.

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