Cadre Codesign Creates JPEG Compression IP Core for FPGA-based Cameras

2/17/2005 - Cadre Codesign Inc.(CCI), a developer and designer of FPGA-based intellectual property (IP) core for signal and image processing applications, announced it has completed the development of a high performance JPEG compression IP core, the CTJPEG-04, for FPGA-based intelligent cameras. Capable of sustaining 500 frames per second at a resolution of 1280 by 1024 pixels, this compression engine was customized from CCI's IP core library to fit FastVision - New Hampshire USA - FastCamera13TM and FastCamera40TM.

Based on the JPEG ISO/IEC IS 110918-1 standard image compression algorithm, the design supports a continuous data flow, and can be used in the most stringent video compression applications without the support of a host or a co-processor. The implementation enables images captured by FastVision's cameras to be compressed through a configurable user interface and to be transmited to a host via a USB-2 standard interface. The core is fully synchronous, autonomous and offers a localized graceful image degradation when the high frequency content in the processed images is too high.

"We strongly believe that the industrial camera market is rapidly shifting towards intelligent cameras with more embedded processing. We strongly believe that the industrial camera market is rapidly shifting towards intelligent cameras with more embedded processing. We strongly believe that the industrial camera market is rapidly shifting towards intelligent cameras with more embedded processing," said Pierre Popovic President of Cadre Codesign. "While some of these so called smart cameras are beginning to appear on the market, vendors, have not fully exploited possible applications and the development of IP cores that can be implemented on FPGAs, and this is where our FPGA image processing design expertise come into play."

The input to the JPEG IP core comes from a Micron Imaging type sensor at a pixel rate of 10 pixels of 10 bits on every cycle of a 66 MHz clock. Image samples are frequency transformed using a discrete cosine transform with an 18-bit internal accuracy and fed through one of two Huffman and a quantization tables, which are configurable at any time during compression.

"FastVision believes that the move to inexpensive open interface standards for most high-speed camera application is unavoidable" said Joe Sgro, President and CEO of FastVision LLC. "As a leading supplier of CMOS based high speed cameras, FastVision intends to be on the forefront of new technological solutions to the userís problems of speed and cost."

The CTJPEG-04 does not require any external memory and was developed to be implemented on Xilinx Virtex XC2V2000 field programmable gate array (FPGA). The core outputs JPEG-JFIF or motion JPEG compressed data which can be converted back to standard image formats at the host. CTJPEG-04 is also available in different configurations accepting variable number of pixels per cycle and pixel resolutions.

About Cadre Codesign Inc.
Cadre Codesign is a Montreal Canada-based company which focuses the research, development and marketing of high performance computing technologies. Incorporated in 2000 Cadre focuses on ways to accelerate - in hardware - the execution of compute intensive algorithms, especially those associated to imaging and analysis algorithms. That led the company to develop its own prototyping hardware, EDA tools, design methodologies, IP librarries of image processing cores. Most of the development ideas at Cadre are the result of R&D where the company is continually investing time and resources.

About FastVision LLC
FastVision is a new hight-speed smart camera producer. Their goal is to bring down the high cost of high- speed image acquisition and make the use of new CMOS and Interconnect technology. The result of this approach is to introduce innovative and cost effective solution to the broad machine vision and military markets.

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