Celoxica Debuts ESL Implementation Flow for SoC Prototyping, Verification

2/15/2005 - Celoxica, the leading provider of C-based Electronic System Level (ESL) behavioral design and synthesis solutions, announced it is shipping Agility Compiler for SystemC to customers. The v1.0 tool includes an array of advanced system design capabilities for the synthesis of SystemC models to hardware. The tool produces IEEE compliant RTL descriptions as input to popular ASIC/ SoC synthesis flows, and generates gate-level EDIF netlists for high-density programmable logic devices.

With Agility Compiler, designers can produce working silicon from SystemC models much earlier in the design flow, accelerating system verification and SoC prototyping. The direct path from SystemC to hardware closes a critical gap in the ESL design flow for successful SoC design from system-level models.

Agility Compiler synthesizes a complete hardware system with no artificial limitations on design hierarchy, structure, timing or interfaces. Agility Compiler advanced synthesis technology supports multi-million gate designs, multiple blocks and multiple clock domains, easily beating the results of entry-level behavioral synthesis tools that restrict designers to small, single block, single clock domain designs. In addition, Agility Compiler synthesis extracts accurate timing and physical design metrics to support fast cycle accurate simulation and test bench generation for system verification.

Early SoC prototypes
By allowing SystemC Transaction Level Models (TLM) to be automatically synthesized to RTL descriptions or FPGA netlists, system models are realized in FPGA based SoC prototypes much earlier in the design flow.

"Agility Complier drastically reduces the risk inherent in complex SoC design and enables designs to be turned around to meet a much shorter market window," said Jeff Jussel, vice president of marketing for Celoxica. "The ability to synthesize from transaction level models tightens the link between the algorithm specifications, the system verification software, and the end hardware."

Agility Compiler's synthesis is driven from pure, standard compliant SystemC descriptions. By avoiding the use of proprietary descriptions or linked constraints, the synthesizable SystemC code remains standard compliant and portable for model and IP reuse. Agility Compiler is fully compliant with the OSCI standard SystemC synthesizable subset.

The Agility Compiler gate-level synthesis supports very high-density FPGA devices, such as Altera's Stratix II and the Virtex 4 family from Xilinx with advanced synthesis features such as re-timing, fine-grained logic sharing, dead-code elimination, rewriting and automatic tree balancing. This direct synthesis support enhances Agility Compiler's applicability to SoC prototyping, accelerated verification and rapid system implementation.

About Celoxica
An innovator in ESL design, Celoxica supplies the design technology, IP and services that define software-compiled system design, a methodology that exploits higher levels of design abstraction to dramatically improve silicon design productivity. Celoxica's products address hardware/software partitioning, co-verification and C-based synthesis. Established in 1996, Celoxica offers a proven route from complex algorithms to hardware, and provides a portfolio of ESL design tools that deliver significant productivity advantages for digital signal processing applications such as imaging, electronic security and communications. For more information, visit: www.celoxica.com.

Celoxica and the Celoxica logo are trademarks of Celoxica, Ltd.

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