TransEDA Enhances Coverage Accuracy with Expression Coverability

2/15/2005 - TransEDA, the leader in coverage and ready-to-use verification solutions for electronic hardware designs, announces the introduction of Expression Coverability - a major addition to the existing, proven capabilities of their established Verification Navigator suite of HDL verification tools.

What is Expression Coverability Analysis?
Measurements of statement and branch coverage are no longer considered sufficient for the verification of HDL design representations. Achieving even 100% statement and branch coverage does not ensure that a design has been sufficiently exercised. Best Practice now demands the use of coverage for expressions in conditional statements, which requires analysis at a greater level of detail.

Using technology that has been proved by aerospace industry experts to be equivalent to Modified Condition/Decision Coverage (MC/DC), mandatory in safety-related applications, TransEDA’s established Focused Expression Coverage (FEC) metric delivers this ultimate level of accuracy.

To boost the effective use of FEC, TransEDA introduces Expression Coverability Analysis, a new feature that augments the Coverability Analysis capability of the Verification Navigator tool set.

Expression Coverability provides automatic and in-depth analysis of conditional expressions for designs written in Verilog, VHDL and mixed languages.

Automatically and transparently using the power of an embedded formal engine, uncoverable expression terms, and coverable terms that have not been exercised, are quickly identified.

After confirmation, uncoverable expression terms are eliminated from the overall coverage calculation.

Diagnostic information, including VCD files, is generated for currently uncovered, but testable sub-expressions, allowing engineers to concentrate the verification effort on productive tasks that will reduce the time to sign-off.

Easily integrated into any existing design flow, VN-Cover with Design Coverability Analysis – including Branch and Expression Coverability - will deliver greater verification confidence through highest accuracy metrics, in reduced time-scales.

Design Coverability Analysis is available now as an option to VN-Cover on platforms running Solaris or Linux operating systems.

For more information, a demonstration or an evaluation copy, contact your local representative or visit

About TransEDA
TransEDA is a leading provider of coverage and ready-to-use verification solutions for electronic designs. The company has over twelve years operating experience in the EDA market. TransEDA provides advanced verification and verification closure measurement solutions including code coverage with coverability analysis capability, specification coverage and impact analysis, configurable HDL rule checking with automatic formal checks, static assertion verification, automatic bus protocol checking, verification IP with bus-based system-level test automation, test suite optimization and transistor-level functional abstraction.

TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, plus local representatives in China, India, Korea, Singapore and Taiwan. For more information, visit

TransEDA, the TransEDA logo and Verification from Concept to Reality are registered trademarks of TransEDA Technology Ltd.

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