Renesas Introduces SH-Mobile3A Mobile Phone Application Processor

2/11/2005 - Renesas Technology Corp. announced the SH-Mobile3A (SH73380), a new edition to the SH-Mobile series of mobile phone application processors. The device offers the latest multimedia processing features, including support for terrestrial digital TV broadcasts and 5-megapixel camera modules, and a JPEG hardware accelerator for still images. This makes it ideal for use in high-end mobile phones.

The SH-Mobile3A incorporates the newly developed VPU4 video processing IP. This provides high speed processing support for the video compression standards H.264 adopted for ISDB-T, a 'one-segment broadcasting' system for delivering terrestrial digital TV broadcasts to portable devices, and MPEG-4 used for movie and videophone applications. The VPU4 is capable of decoding VGA size video at a rate of 30 frames/second (f/s). Furthermore it incorporates a transport stream interface that allows separate processing of video and audio data without CPU load. The device can also support multiple digital TV broadcasting formats for mobile phones, including DVB-H and DMB.

The VPU4 incorporates 7-stage pipeline processing technology that reduces power consumption either through the use of lower clock frequencies or through dynamic variation of the clock numbers of the individual stages. As a result, current consumption by the IP core while operating at 66 MHz is only approximately 36 mA when decoding VGA size video at a rate of 30 f/s.

The SH-Mobile3A is equipped with a camera interface that supports direct connection to a 5-megapixel camera module (the highest resolution supported by the SH-Mobile series) and incorporates image processing functions. The interface allows large volumes of image data to be captured and displayed with a variety of options, including digital zoom and overlay using on-screen display (OSD) and hardware cursor (HWC) functions, for example. The SH-Mobile3A also includes a video output unit compatible with NTSC and PAL, allowing the mobile phone to be connected to a TV to display high-resolution images captured using the mobile phone's built-in camera.

The processor is the first device in the SH-Mobile series to incorporate a newly developed JPEG hardware accelerator. This realises a maximum still photo successive capture speed of 0.02 seconds/photo or better for VGA size and 0.1 seconds/photo or better for SXGA size. This makes the creation of a wide range of attractive camera applications possible by allowing users to take photos in rapid succession.

The SH-Mobile3A is based on the SH4AL-DSP CPU core that offers a processing performance of 389 MIPS at a maximum operating frequency of 216 MHz. This gives a performance by frequency unit of 1.8 MIPS/MHz, enough to handle a browser for viewing one-segment broadcasts. This capability also enables the device to handle parallel processing of multiple high load applications and operations using a general purpose OS such as Linux for a greater processing load than a dedicated OS.

Additionally, the SH-Mobile3A offers a variety of peripheral functions ideal for mobile phone systems, including an LCD controller compatible with TFT colour LCD panels and a sound interface. The device is available in a 409-pin CSP package (12 mm x 12 mm x 1.4 mm, 0.5 mm pin pitch). Sample shipments will begin in April 2005.

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About Renesas Technology Corp.
Renesas Technology Corp. designs and manufactures highly integrated semiconductor system solutions for mobile, automotive and PC and Audio Visual markets. Established on April 1, 2003 as a joint venture between Hitachi, Ltd. (TSE:6501, NYSE:HIT) and Mitsubishi Electric Corporation (TSE:6503) and headquartered in Tokyo, Japan, Renesas Technology is one of the largest semiconductor companies in the world and the number one microcontroller supplier globally. Besides microcontrollers, Renesas Technology offers system-on-chip devices, Smart Card ICs, mixed-signal products, flash memories, SRAMs and more.


ItemSH-Mobile3A Specifications
Product nameSH73380 (R8A73380BG)
Power supply voltageInternal: 1.1 V to 1.3 V
External: 2.5 V to 3.3 V or 1.65 V to 1.95 V
Maximum operating frequency216 MHz
Maximum processing performance389 MIPS (at 216 MHz operation)
On-chip RAM128 Kbytes
Cache memory4-way set associative type, with separate 32 Kbytes for instructions and 32 Kbytes for data
X/Y memory (for DSP)16 Kbytes
On-chip peripheral functions
  • 5-megapixel camera support functions
  • VPU4 (H.264/MPEG-4 full hardware accelerator)
  • JPEG hardware accelerator
  • 2-D/3-D graphics engine
  • DMAC 6 channels
  • MMU
  • Video output unit (NTSC/PAL)
  • LCD controller supporting TFT color liquid crystal display
  • USB function (USB 2.0 full speed compatible)
  • Interfaces
  • Dedicated interface (connection to baseband LSI, etc.)
  • Transport stream (TS) interface
  • NAND/AND flash memory interface
  • Video I/O (direct camera module connection interface)
  • I2C* interface
  • Clock-synchronous serial interface 1 channel
  • Serial interface with FIFO 2 channels
  • Asynchronous serial interface 4 channels
  • Sound interface unit 2 channels
  • Key scan interface
  • Package409-pin CSP (12 mm 12 mm 1.4 mm, 0.5 mm pin pitch)

    *I2C (Inter IC Bus) is an interface specification proposed by Royal Philips Electronics of the Netherlands.

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