Denali Forms RDL Alliance to Promote Register Description Language

12/20/2005 - Denali Software announced the formation of an industry alliance to promote industry-wide adoption of a Register Description Language (RDL) in the development and delivery of intellectual property (IP) used in system-on-chip (SoC) designs.

The RDL Alliance will benefit IP providers and system developers by giving them a common, consistent and computer-readable for describing configuration registers to speed a chip's architecture, design, verification and documentation.

Charter members Mentor Graphics Corp., MIPS Technologies Inc., and Rambus Inc. have agreed to use RDL for the design and delivery of select IP products.

Other members will be named as they join the alliance.

"It is critical for the semiconductor industry to address chip design productivity, from architecture and design through verification and software development," remarks Mark Gogolewski, Denali's Chief Technology Officer (CTO), and chair of the RDL Alliance. "This is particularly true for IP-based methodologies which are now the norm for most chip designs. This alliance represents a pragmatic approach to streamlining SoC development. We've created a practical program that offers immediate gains in productivity to IP providers and consumers, without requiring a methodology overhaul."

Alliance Benefits for IP Providers
Configuration registers exist in all semiconductor chips and IP products, and often number in the thousands. These registers store key parameters that define the chip's operation and are required by system architects, hardware developers and software engineers to develop end products.

The RDL Alliance will benefit commercial IP vendors in two dimensions. For IP development, alliance members gain access to Denali's BlueprintTM product which takes RDL input and automatically generates documentation, register designs in Verilog or VHDL, as well as models for verification and software development.

The auto-generation of all necessary register views through Blueprint provides productivity gains for IP design and increases overall quality through a correct-by-construction methodology.

Alliance members also benefit from improved quality and reduced cost for customer support. Blueprint, a third-generation register-management technology used successfully in numerous large SoC designs, provides an abstraction layer that insulates customers from design or architectural changes during IP modifications or derivative designs.

The abstraction layer creates a stable environment for early hardware and software development. Blueprint also enables IP vendors to auto-generate outputs that support various methodologies and third-party development tools used by their customers.

Notes Sean Smith, Chief Verification Officer at Denali: "We're solving real-world problems and active participation from experienced IP providers such as Mentor Graphics, MIPS and Rambus is a testament to the value of this program.

I am a champion of advancing state-of-the-art for design and verification, and we continue to promote reuse methodologies through our products and technology. Sometimes automating simple steps can lead to tremendous impact on productivity and efficiency throughout the design chain.

The industry is getting better at recognizing the value of tools and methodologies that span across the traditional scope of EDA to software, test and documentation.

The RDL Alliance supports one such solution and, with the support of IP vendors, makes it easy to deploy across the industry."

"We believe the RDL Alliance and its access to Blueprint for IP product development will lessen the burden of IP integration for SoCs, a major factor in post-sales support " stated Jim Venable, Mentor Graphics IP Division Director of IP products.

"The electronic design community should benefit from RDL standardization with easier IP integration and design reuse, cost reduction, and improved product development schedules."

Alliance Benefits for IP Consumers
Control registers found in an IP or chip design defines the software interface to the chip and usually represents the largest portion of the chip specification or programmers guide.

Vendors delivering RDL with their IP products will give their customers instant access to customizable views of registers for internal hardware design, software development and documentation.

This eliminates the need to manually redevelop register views to conform to internal requirements from various development teams.

Because SoC developers typically integrate multiple IP cores from multiple vendors, the availability of consistent, high-quality register views speeds integration of third-party IP, increases design efficiency and reduces the overall cost of IP deployment.

For more information on how to join the RDL Alliance, or how to benefit from the RDL Alliance community, visit

About Denali
Denali Software Inc. is the world's leading provider of Engineering Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's DatabahnTM and DataplexTM IP products provide control and optimal data throughput for external DRAM and Flash memory devices.

The PureSpecTM and MMAVTM verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, ASI, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's BlueprintTM product provides a complete solution for on-chip register design and management. Call +1 (650) 461-7200, or email:

Blueprint, Denali, the Denali logo, Databahn, Dataplex, PureSpec and MMAV are trademarks of Denali Software Inc.

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