Cadence RF Design Methodology Kit Addresses Wireless Design Challenges

12/13/2005 - Cadence Design Systems, Inc (NASDAQ: CDNS) announced the Cadence® RF (Radio Frequency) Design Methodology Kit, targeted to address key challenges in wireless design. The new kit addresses challenges in a burgeoning technology sector. RF transceivers are a core component of all wireless devices, and a 2005 Gartner report predicts wireless IC demand will reach $46.1 billion by 2006. The Cadence RF Design Methodology Kit helps wireless chip designers achieve shorter, more predictable design cycles by better ensuring that silicon performance matches design intent.

"The Cadence kits approach is very valuable and will benefit many wireless companies," said Gianmaria Mazzucchelli, vice president of Engineering, Nemerix. "Having a properly estimated and predicted system up front ensures that you have the whole wireless system under control. There are many techniques peculiar to wireless, and a design kit with recommendations on methodologies and tools is definitely a benefit."

The Cadence RF Design Methodology Kit leverages the latest technologies from Cadence for intelligently managing parasitic extraction and linking system-level design with IC implementation, and accurately, yet rapidly, verifying complete wireless designs that span digital, analog and RF.

The kit includes an 802.11 b/g WLAN transceiver reference design, a full suite of RF verification IP, test plans, and applicability training on the RF design and analysis methodologies. The kit focuses on front-to-back RF IC design and addresses behavioural modelling, circuit simulation, layout, parasitic extraction and resimulation, and inductor synthesis. It also focuses on IC verification within a system context, leveraging system-level models and testbenches for use by designers in the IC environment.

The Cadence RF Design Methodology Kit leverages accurate 3D extraction technology and advanced physical modelling capabilities from AssuraTM RF, links to system-level environments, and key new functionality in the Virtuoso® custom design platform with Flexible Balance option for calibrated results of transient and frequency analysis. The Virtuoso AMS Designer link to MATLAB and Simulink from The MathWorks is an example of a link to a key system-level design tool. The link to MATLAB and Simulink provides an executable specification that is continually elaborated throughout the development process. Thus, a common environment can be leveraged as IC designers verify against a system-level specification across multiple domains including system, digital, mixed-signal, and analog RF.

"With the link between Virtuoso AMS Designer and our MATLABand Simulink products, system designers and IC designers can now identify design and integration problems earlier in the design cycle," says Jim Tung, MathWorks Fellow at The MathWorks. "And by offering a viable path from system-level design to IC implementation and verification, and using a golden reference Simulink model through that process, a Model-Based Design approach can be leveraged effectively across the stages of a design."

The announcement of the Cadence RF Design Methodology Kit follows on the heels of the Cadence AMS Methodology Kit and the Cadence Optimization Kit for ARM Processors, which Cadence announced at CDNLive! 2005.

"Our customers continue to meet the market demands for ICs with wireless functionality, integrating voice and data capability with less power at a lower cost and within a shorter timeframe," said Ajay Malhotra, senior vice president of Marketing at Cadence. "We have seen tremendous customer interest in Cadence's kits approach and customers can expect more Cadence kits in the near future in areas of networking and consumer electronics."

More information about the Cadence RF Design Methodology Kit is available at

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry.

Cadence, the Cadence logo, Assura and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the U.S. and other countries.

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: