12/6/2005 - Cadence Design Systems, Inc. (NASDAQ:CDNS) announced Cadence® Encounter® Conformal® Low Power GXL. This latest Encounter Conformal configuration provides the final tier of the Encounter segmentation strategy unveiled in September and is set to extend the lead that Cadence holds in formal verification. This includes important new technology to help customers validate power critical designs such as verification of aggressive low-power and synthesis optimizations, to target the challenges of advanced designs at 65 nanometers and beyond.
As customers create highly integrated devices for processes at 65 nanometers and beyond, they must design for low power to extend the battery life of hand-held devices, and to reduce system power and package costs in wired devices. Significant transistor leakage can occur at these smaller process nodes, and new design techniques are required to reduce dynamic and static power losses.
As customers adopt new tools and methodologies to address low-power design challenges, it is critically important that they are able to verify the correct implementation of low-power design techniques. Encounter Conformal Low Power GXL provides a unique combination of transistor abstraction, equivalency checking, and functional verification technology that enables customers to verify low-power designs.
"We've seen many of our client companies starting multi-supply voltage designs to meet the more aggressive challenges for low power," said Nobu Nishiguchi, Vice President, General Manager Development Dept.-1 of STARC. "STARC has adopted Conformal Low Power technology in STARCAD-21, our production flow for SoC designs for nanometer process nodes. We were impressed by the effective use of the formal verification technology that Conformal Low Power provided, with both functional and structural checks on RTL and physical netlists."
Encounter Conformal Low Power GXL can fully verify the correct implementation and functionality of low-power design techniques such as state retention and isolation. Its transistor analysis capabilities ensure that standard cells and custom cells correctly control leakage and perform intended isolation functions. Encounter Conformal Low Power GXL also checks that logic is mapped to the correct physical power domains in a design. Its industry-leading formal verification engines help functionally verify that circuits are in the correct state to perform isolation and state retention.
At 65 nanometers and beyond, substantial leakage current can flow through unintentional transistor circuit paths known as 'sneaky paths'. Encounter Conformal Low Power GXL is able to efficiently find these paths, allowing designers to make corrections and save significant power.
"Users tell us that Encounter Conformal Low Power GXL is the best formal verification technology on the market," said Michael Chang, corporate vice president, R&D for Cadence. "Encounter Conformal Low Power GXL decreases the verification cycle, improves quality of silicon (QoS) and speeds up time to market. Cadence continues to lead the technology charge at 65 nanometers and beyond."
Cadence product segmentation strategy, announced at CDNLive! in September, provides customers with multiple levels of technology tailored to specific levels of design complexity. Cadence design platforms now offer a tiered range of products scaled to different complexities of digital IC design.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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