Lattice Rolls Out ispLEVER 5.1 Programmable Logic Design Tool Suite

11/2/2005 - Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of its ispLEVER® 5.1 programmable logic design tool suite. Version 5.1 implements many new features and delivers enhanced performance. For example, Lattice FPGA logic utilization has been increased by as much as 35%, while design operating frequencies have been boosted up to 25%. A new IP delivery infrastructure called IPexpressTM is included that allows designers to quickly configure Lattice system-level IP for their designs. The ispLEVER 5.1 release also introduces significant improvements to the FPGA design process, allowing designers to work more efficiently, improve productivity and speed time to market.

New FPGA Design Preference Flow
The ispLEVER 5.1 software introduces a new FPGA design preference flow that gives more control to the designer. Design preferences that dictate how an FPGA design will be implemented in Lattice silicon are no longer tied to a particular stage in the design process. The FPGA designer can make changes to design preferences at any point, from the initial stage of HDL source code to final place and route, and is assured of greater consistency throughout the entire design process. "The new IPexpress infrastructure and our new FPGA design preference flow are two significant design productivity improvements that transform our ispLEVER software into a more powerful tool for our customers," said Chris Fanning, Lattice vice president of software and IP solutions. "Our customers face tremendous time to market pressures and ispLEVER 5.1's enhanced flow and performance capabilities will significantly improve their productivity and results."

Improved design performance
The ultimate measure of design tools performance is the quality of design results. The ispLEVER 5.1 software introduces significant improvements in the maximum operating speed of designs (fMAX average), as well as the efficiency of silicon resource usage (LUT and SLICE utilization). Using techniques that include timing-driven mapping and congestion-driven placement, device logic resource usage has been reduced by as much as 35%, and silicon performance increased up to 25%. These improvements can ultimately translate into lower-cost solutions for customers, as their designs can frequently fit into smaller and lower speed grade Lattice FPGAs. "Performance and utilization improvements in ispLEVER 5.1 further enhance our world-class FPGA design solution," said Stan Kopec, Lattice vice president of corporate marketing. "The performance and productivity gains enabled by ispLEVER 5.1 ensure that our customers can achieve their design goals more easily and at lower cost."

Industry Leading Synthesis and Simulation
Lattice continues to be the only programmable logic company to include industry-recognized best-in-class synthesis and simulation tools with every Windows-based ispLEVER installation. Ongoing collaboration among Lattice and EDA industry leaders Synplicity and Mentor Graphics provides HDL synthesis and simulation tools optimized for Lattice products. The ispLEVER 5.1 release includes new versions of Synplicity® Synplify® for Lattice (v8.2c), and the Mentor Graphics® Precision®RTL (2005b) synthesis tools, as well as the Mentor Graphics ModelSim® version 6.1a simulation tool.

The ispLEVER 5.1 software also includes new device libraries that expand support for additional EDA tools, including simulation tools from Cadence® (NC-Verilog®) and Synopsys® (VCS®), and new DSP design elements for the MATLAB®/Simulink® design environment from The MathWorks.

IPexpress Infrastructure
Intellectual Property (IP) cores are now commonly used in FPGA designs. The ispLEVER 5.1 software includes a new infrastructure that will dramatically improve the way Lattice customers access and utilize IP. The IPexpress infrastructure will allow users to parameterize IP quickly and easily, without factory assistance. The IPexpress infrastructure provides a single easy-to-use gateway to industry standard, user-configurable functions that have been optimized for maximum performance in Lattice silicon products.

Dozens of Improvements to All ispLEVER Tools, Including:

A complete list of the new features and enhancements to the ispLEVER 5.1 design tool suite can be viewed at

Availability and pricing
The ispLEVER 5.1 software for Windows, supporting all Lattice digital programmable logic families, is list priced an industry best value of $695 and is available immediately. UNIX and LINUX versions also are available.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC®) and Programmable Digital Interconnect Devices (ispGDX®). Lattice also offers industry leading SERDES products.

Lattice is "Bringing the Best Together" with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and "single chip solution" space savings. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), IPexpress, ispGDX, ispLEVER, ispPAC, LatticeXP, MachXO and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

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