Aldec Rolls Out Active-HDL 6.3, Altera Edition

1/26/2005 - Aldec, Inc., a pioneer in mixed-language simulation and advanced design tool company for ASIC and FPGA device development, announced the release of Active-HDL 6.3, Altera Edition with direct support and automation for Altera’s Quartus® II design software version 4.2, Stratix® II FPGAs and HardCopy® II structured ASICs.

Complete FPGA and Structured ASIC Prototyping Solution
Aldec has developed a Tcl-based script that automates the design flow interface between Active-HDL and the Quartus II software. This automated solution from Aldec and Altera provides the engineer with a closed design environment while delivering complete access to compile and simulate FPGA and HardCopy structured ASIC devices from a single design environment.

“Active-HDL’s Altera Edition with Quartus II software support provides the designer with full access to unlimited simulation and debugging capabilities for FPGA and structured ASIC designs in an easy-to-use environment,” stated Chris Erwin, product marketing manager for Aldec, Inc. Erwin added, “The automated Design Flow Manager, along with precompiled Altera libraries and access to several popular synthesis tools, completes the solution.”

“Active-HDL, Altera Edition and Quartus II software provide a cohesive design solution for customers targeting high-performance Stratix II devices. This design solution is also applicable to the recently announced HardCopy II structured ASIC,” said Jim Smith, director of EDA vendor relations at Altera Corporation.

Design Flow Manager
Active-HDL’s Design Flow Manager handles the entire process from design capture through synthesis, implementation and optimization including a direct link to the Altera Megafunctions Wizard. The Altera Quartus II physical implementation tools can be easily be accessed and automated by the Design Flow Manager and provides centralized error message handling with direct access to the synthesis and implementation reporting. Active-HDL’s Memory Viewer can also read and save Altera Memory Initialization Files (*.mif).

About Active-HDL
Active-HDL is a Windows®-based, completely integrated, high performance HDL design and simulation environment. It supports VHDL, Verilog, SystemC and EDIF from design entry through implementation. Active-HDL provides the fastest simulation runs for all designs, regardless of source language or target silicon, including those with embedded devices.

The product conforms to IEEE standards for VHDL and Verilog and provides a complete Altera FPGA solution. Active-HDL 6.3 AE, which is available today, includes a multi-design workspace, HDL editor, state machine editor, block diagram & schematic editors, automatic testbench generation, simulation design profiler, signal agent, waveform viewer, SystemC and a choice of VHDL, Verilog or mixed-VHDL/Verilog/EDIF simulation. Active-HDL 6.3 AE is sold directly from Aldec and all sales include one year of product maintenance. For a FREE evaluation copy, please visit our company’s website at

About Quartus II Design Software
Altera’s Quartus II design software is the industry’s most technologically advanced development software for FPGA, CPLD, and structured ASIC designs. The Quartus II design software includes a suite of advanced system-level design features, access to Altera’s extensive intellectual property portfolio, an advanced place-and-route engine including physical synthesis optimization technology, and comprehensive verification solutions. Quartus II software also integrates seamlessly with all leading third-party synthesis and simulation tools. For more information about Quartus II design software, visit A free version of the software, Quartus II Web Edition, can be downloaded from the Altera web site at

About HardCopy II Structured ASICs
Altera’s HardCopy II structured ASICs feature a unique FPGA front-end design methodology and deliver the fastest time-to-market and the lowest risk of any structured ASIC solution. HardCopy II structured ASICs leverage Stratix II FPGAs for prototyping and system verification, and deliver up to 2.2 million ASIC gates, 8.8 million bits of RAM, and over 350-MHz system performance at a cost as low as $15 for 1 million ASIC gates. HardCopy II structured ASICs are the best solution for a broad range of high-performance, high-volume ASIC and ASSP applications including wireless, computer and storage, consumer, and industrial systems. For more information about HardCopy II structured ASICs, visit

About Aldec
Aldec, Inc., a 20-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at

Active-HDL is a trademark of Aldec, Inc.

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: