1/18/2005 - Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) announced the release of Encounter(tm) Conformal® Constraint Designer, which automates the generation and validation of design constraints at all stages of the design process from RTL to final netlist. The new product performs comprehensive design constraint quality checks to ensure that designers start with high-quality constraints up front. This helps reduce the number of iterations due to invalid constraints.
Design constraints are used to direct synthesis, timing analysis and place and route to meet a chip's timing, area and power requirements. Poorly designed constraints lead to long implementation design cycle time and the risk of silicon failure and re-spins. With design constraints getting larger and more complex, designers are spending significant amounts of time attempting to produce a set of valid constraints. Until now, there has been no automated solution dedicated to resolve this problem. Encounter Conformal Constraint Designer addresses the challenges of the new domain of constraint design by generating and validating design constraints, and helping pinpoint the root cause of constraint problems.
"We found Encounter Conformal Constraint Designer to be valuable in helping measure the quality and completeness of constraints across several large blocks of our highest-performance desktop graphics chip," said Karl Pfalzer, staff engineer, Desktop Graphics Group, ATI Santa Clara. "The well-designed interface, consistent with the other Encounter Conformal tools, greatly eased the learning curve. As we embark on our next chip and integrate large portions from several design sites, a quick and easy-to-use measure of constraint quality is a must. We expect Encounter Conformal Constraint Designer to become an integral part of our design flow."
Encounter Conformal Constraint Designer is the only complete solution available for ensuring valid timing constraints are met throughout the entire design process. Based on a world-class formal verification engine, it automates the validation and generation of constraints. Pinpointing real design issues quickly, it also helps accurate achievement of rapid timing closure.
"Encounter Conformal Constraint Designer is the latest innovation in Cadence formal verification technology," said Michael Chang, vice president of R&D of Cadence Formal Verification division. "With this new product, customers finally have an integrated approach to address their constraint challenges."
Using this technology, designers reduce overall design cycle times and design risk associated with constraints. Designers also benefit from higher-quality timing constraints for their design implementation, which can significantly enhance quality of silicon (QoS). It provides a vast improvement over conventional inefficient manual constraint validation and modification methods.
Encounter Conformal Constraint Designer is shipping now.
Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centres, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com.
Cadence, the Cadence logo, and Conformal are registered trademarks of Cadence Design Systems in the United States and other countries. Encounter is a trademark of Cadence Design Systems.
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