9/17/2004 - Mentor Graphics Corporation (Nasdaq: MENT) announced that it has enabled the industry's most accurate simulation of nanometer technology with the introduction of new resistance and capacitance engines for its full-chip, transistor-level parasitic extraction solution, Calibre® xRC.
Based on the new resistance engine, Mentor Graphics has also developed hierarchical netlisting and optimized back annotation capabilities between Calibre xRC and Nassda's high-performance simulation platform HSIMplus.
"Our designs require the most sophisticated methods available to model the behavior of advanced manufacturing technologies," said Karl Johnson, senior CAD engineer, Centaur Technology. "Calibre xRC coupled with Calibre LVS allows us to accurately and efficiently capture the 90nm effects, and deliver data to our downstream timing analysis and signal integrity flows at both the gate and transistor level."
The shrinking geometries and increased design sizes prevalent today have created greater chip functionality, but have also taken some of the predictability out of modeling at the device level. For example, to accurately model the behavior of a transistor, the number of parameters has grown significantly beyond simple length, width and area.
Nanometer effects can cause an entire chip to fail, and must be correctly accounted for in post-layout simulation and analysis to ensure acceptable yield. Calibre xRC's new resistance and capacitance engines, combined with Calibre LVS (layout vs. schematic) fully comprehend the boundary of the BSIM4.0 simulation model to accurately measure, extract and analyze these new parasitics in a geometrically accurate way with smaller netlists, helping to preserve performance, capacity and yield.
Calibre xRC's new resistance and capacitance engines offer several advantages. The resistance engine provides better fracturing, including precise width and resistor location for electro migration analysis. It also offers enabling technologies for inductance extraction and improved device pin handling, improved gate pin placement and user control over gate region extraction. Additionally, the algorithms are hierarchical and much more efficient. Better performance and capacity is attained using the new paradigm while still providing improved accuracy.
Calibre xRC's new capacitance engine delivers a much tighter correlation to field solver and silicon data, greatly improving overall accuracy of results. In addition, it has incorporated special models for vias, contacts and the poly-to-contact area, as these are quite susceptible to significant and elusive capacitance effects. Other solutions are taking mathematical shortcuts to modeling that will get them quick extraction results, but will break down later in the design flow. Calibre xRC gives designers greater confidence in their post-layout simulation results, and therefore they do not have to build in prohibitive design margins.
"A comprehensive approach to nanometer silicon modeling is an essential part of a complete DFM design flow," said Joe Sawicki, vice president and general manager, Design-to-Silicon Division, Mentor Graphics. "Based on silicon results, we are confident that Calibre's new resistance and capacitance engines address yield limiting factors in nanometer technology."
Calibre xRC and Nassda HSIMplus: Better Together
The collaboration between Mentor and Nassda gives designers the ability to efficiently simulate large, complex nanometer designs. Calibre xRC DSPF data structures and extraction algorithms, optimized for Nassda's preferred flow, enable users to experience high degrees of accuracy and performance.
"Calibre xRC is a unique extraction solution that provides parasitic data in a true hierarchical format which is needed for verification of complex designs," said Graham Bell, senior director of marketing, Nassda. "Our mutual customers will see a dramatic improvement in the efficiency of extraction and simulation using this combined flow. With much greater capacity, they will be able to perform accurate post-layout analysis and verify the impact of nanometer silicon on design performance which can improve chip yield."
Calibre is the first full-chip, hierarchical parasitic extraction solution. HSIM provides detailed circuit-level simulation of timing and power behavior and signal integrity effects. Used by more than 250 companies including the top 25 semiconductor companies, it enables first silicon success and dramatically improved product quality. As part of the HSIMplus verification platform, it solves the critical issue of analyzing circuit behavior while taking into account the electrical and parasitic effects of nanometer-scale silicon.
Pricing and Availability
Pricing for Calibre xRC starts at $148,000. Calibre xRC runs on Solaris, HP and Linux.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $675 million and employs approximately 3,800 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation.
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