Lattice Hosts Web Seminar on Easy DDR Memory Interface Design in FPGAs

7/27/2004 - Lattice Semiconductor Corporation (NASDAQ: LSCC) will conduct a net seminar on the easy design of DDR memory interfaces in FPGAs. More and more systems are taking advantage of economical double data rate (DDR) memories, but DDR memory interface design can be tricky, particularly at 200DDR (100MHz) speeds and higher. The new LatticeECPTM and LatticeECTM low-cost FPGAs provide unique pre-engineered DDR memory interface solutions that are easy and reliable. Attendees will learn how to design DDR interfaces that are high-performance, accurate, reliable, voltage- and temperature-compensated and pre-engineered. Those attending the net seminar live who complete the post-presentation survey will be entered in a drawing for an ispLEVER® Development Tool for Lattice FPGA and CPLD design ($995 USD value).

Bertrand Leigh, Applications Engineering Manager, Lattice Semiconductor

Wednesday, July 28, 2004 at 10:00 a.m. PDT

Online Net Seminar
To register for the seminar, please visit

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP, LatticeEC, ispLEVER, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

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