7/26/2004 - Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, announced the United States Patent Office has awarded the company a patent for technology that addresses mounting signal integrity issues in next-generation ICs. This announcement marks Synplicity’s 18 th patent for various technological innovations in the design and development of semiconductors, including FPGA, ASIC and Structured/Platform ASIC devices.
Synplicity’s latest technology achievement, patent number 6,734,472 B2, titled, “Power and Ground Shield Mesh to Remove Signal Coupling Effects,” provides users with increased signal integrity safety, better pre-route delay prediction, power and ground noise suppression and improved power distribution, guarding against unforeseen design issues that could prove costly. The technology described in the patent uses a unique two-dimensional power and ground-interconnect mesh to shield both capacitive and inductive coupling between susceptible signal lines. Synplicity believes this technology will enable the more efficient development of integrated circuits at 90nm and below.
Ken McElvain, chief technical officer at Synplicity, said, “Our broad patent portfolio is a testament to the innovation we have achieved over the past 10 years. Indeed, this newest patent further demonstrates Synplicity’s fervor for technological advancement within the EDA industry. We believe our latest patented technology will bring significant benefits to the semiconductor design community and help minimize signal integrity problems as next-generation integrated circuits are developed in smaller and lower voltage process technologies.”
Unlike current industry methods, which start at an unsafe starting point with complex, and sometimes inaccurate, modeling of aggressor and victim signal interactions followed by an attempt to repair all the signal integrity violations with ad hoc techniques, Synplicity’s patented signal integrity technique has a starting point where simple routing design rules can be used to guarantee signal integrity safety and predictability of delay. The shielding mesh, which is also used as part of the power distribution, can then be optimized while maintaining signal integrity safety.
Synplicity was granted its first patent in 2001 in the area of automatic extraction of finite state machines and has since been issued 17 additional patents in various design technology disciplines, including but not limited to, physical synthesis for both FPGAs and ASICs, ASIC prototyping and source level debugging of FPGA hardware. Synplicity continues its research and development efforts with over 30 additional patents pending.
Synplicity® Inc. (Nasdaq: SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity’s high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, Structured/Platform ASIC and cell-based/COT ASIC designers. The company’s underlying Behavior Extracting Synthesis Technology® (BESTTM), which is embedded in its logical, physical and verification tools, and has led to Synplicity’s top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company’s fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 280 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif.
Synplicity and Behavior Extracting Synthesis Technology are registered trademarks of Synplicity Inc. BEST is a trademark of Synplicity Inc.
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