Aliathon Helps Altera Customers with Multi-Channel SONET/SDH and PDH IP

7/19/2004 - Altera Corporation (NASDAQ: ALTR) announced the addition of Aliathon to the Altera Megafunction Partners Program (AMPPTM). Customers now have access to Aliathon’s advanced range of multi-channel SONET/SDH and plesiochronous digital hierarchy (PDH) intellectual property (IP) cores for communications applications such as edge switches, edge routers, add-drop multiplexers and associated test equipment. The new SONET/SDH framers and PDH mappers allow designers to replace many of their traditional multi-chip designs with single-chip alternatives, saving both cost and power.

Implemented with Altera’s Stratix® FPGA family, the IP cores maintain high speed while minimizing resource usage. A complete mapping of 336 DS1 or 252 E1 signals to an STS-12/STM-4 frame consumes less than 50 percent of an EP1S25 device, yielding the industry’s most compact solution.

“Aliathon’s IP and Altera’s Stratix FPGAs will provide significant advantages over ASSPs in the SONET/SDH and PDH markets,” said Steve McDonald, managing director of Aliathon. “As an AMPP partner, we will be able to provide Altera’s customers with superb solutions for the communications designs.”

“Aliathon’s broad range of IP cores for the communications industry provides great value for our customers in the communications industry,” said Bob Beachler, Altera’s senior director of development kits and AMPP. “Their SONET/SDH and PDH solutions will not only reduce cost and power for their designs, but will also allow them to rapidly develop a reliable solution for their transmission networks.”

Aliathon Building Blocks
Aliathon provides separate receive (RX) and transmit (TX) building blocks for framing and mapping multi-channel payloads to and from STM-1/4 (STS-3/12). The framer and mapper functions are provided separately for maximum flexibility. The cores are capable of handling a variety of structures, including any mix of virtual containers or tributary units. Additionally, when the cores are used for very simple or regular structures, their size will be reduced. All of the cores are designed to bolt together seamlessly. Aliathon also provides full support to any customers wishing to tailor the cores to their particular needs.

About AMPP
The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. AMPP is an alliance between Altera and developers of IP cores that encourages megafunction development for Altera programmable logic devices and HardCopy® structured ASICs. Through the AMPP program, Altera provides technical information, training, IP integration services, certification, and reference marketing to its AMPP partners. Currently, there are over 25 AMPP partners who offer over 180 megafunctions, all verified through Altera’s rigorous “AMPP Approved” process. Customers may automatically request a free evaluation of any of these cores through Altera's megafunction listings at the IP MegaStoreTM web site at

About Altera
Altera Corporation (NASDAQ: ALTR) is the world’s pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.

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