7/12/2004 - Royal Philips Electronics (AEX:PHI; NYSE:PHG) and Target Compiler Technologies announced that Philips started the distribution of an advanced compiler-centric software development kit for the CoolFlux DSP core. The CoolFlux DSP is a new 24-bit ultra-low power DSP core, which will be launched in the Japanese market today at the 2004 Embedded Systems Expo and Conference (ESEC 2004) in Tokyo. CoolFlux DSP core is available for technology licensing from Philips Intellectual Property & Standards (IP&S) and also distributed through the StarIP program in Synopsys’ DesignWare® Library. The software development kit, called “Checkmate for CoolFlux DSP”, was developed by Target Compiler Technologies, and is a processor-specific instantiation of Chess/Checkers, Target’s retargetable tool-suite for the design, programming and verification of flexible processor cores.
Checkmate for CoolFlux DSP contains both programming and verification tools. The programming environment includes Target’s optimizing C-compilation technology complemented with its assembler/disassembler and linking tools, all controlled from an integrated design environment (IDE). The C-compiler offers both ANSI-C and fixed-point support for the CoolFlux DSP, and generates highly efficient machine code that typically eliminates the need for assembly programming, although an assembler is available as well. The verification environment consists of Target’s graphical debugger, which can be connected both to a fast cycle-accurate instruction-set simulator (ISS) and, via a JTAG interface, to the processor hardware on a development board for on-chip debugging. The ISS has extensive support for co-simulation and for SystemC integration.
According to Philips, one of CoolFlux DSP’s distinguishing features is that it is designed for best C compiler performance. “We wanted our new DSP to outperform other solutions, not only in terms of power consumption and cost, but by offering very efficient C programmability at the same time”, said Johan Van Ginderdeuren, business development manager at Philips Digital Systems Labs (PDSL), Leuven, Belgium. “For audio applications, assembly programming has often been deemed mandatory to meet the ultra-low power requirements. However, the CoolFlux DSP product has shown us the key to compiler friendly low-power design, which is the use of retargetable compilation technology”, Van Ginderdeuren added.
Philips PDSL’s team has made intensive use of Target’s Chess/Checkers retargetable tool-suite. Chess/Checkers allowed for quickly modeling the core’s instruction-set architecture in the processor description language nML and for performing architectural exploration and optimization using feedback from the retargetable C compiler and ISS. This way, the CoolFlux DSP’s instruction-set architecture could be matched to the requirements of typical applications, and at the same time efficient C compiler support could be ensured. MP3 decoding and other critical audio functions have been used as driving applications during this design process.
Central to the process was Chess, Target’s retargetable C compiler. “Our patented graph-based compilation technology enables full use of instruction level parallelism, pipelining, and the heterogeneous aspects of embedded processor architectures”, said Gert Goossens, CEO of Target. “This results in highly optimal compiled code, both from a cycle and code density perspective, comparable to hand-optimized assembly code.” Dirk Lanneer, VP Engineering of Target, added: “For CoolFlux DSP, an optimized instruction encoding combined with program memory compression techniques contributed to small footprints in a 32-bit program memory.” Johan David, CoolFlux DSP Technology Manager at Philips Digital Systems Labs, confirmed the efficiency of the C compiler: “As an application example, we have developed the software for the MP3 decoder from C using the Chess C compiler, without any optimizations at assembly level. Only 14.5 MIPS are required to decode a 44.1 kHz stereo signal encoded at 128 kbps, resulting in a power consumption of less than 1 mW in CMOS18”.
To verify the correctness of the register-transfer level (RTL) hardware implementation of CoolFlux DSP, Philips’ engineers furthermore used the Risk tool, a retargetable test-program generator that is part of the Chess/Checkers tool-suite. Using Risk, a large number of assembly-level test-programs for the CoolFlux DSP could be generated quickly, with high fault coverage. These test programs could then be executed both in the ISS and in the RTL model of the processor, to validate consistency.
“The Checkmate toolkit is already being used by CoolFlux DSP’s lead customers and a free evaluation license is available via Philips for one month, also to subscribers of Synopsys’ DesignWareâ Library”, said Tony Picard, Target’s VP Sales and Marketing. “We are pleased to add CoolFlux DSP to our track record of successful projects with Philips, and we are looking forward to serving the CoolFlux DSP user community with our tools, distributed via Philips.”
More info on CoolFlux DSP
For further details about CoolFlux DSP, see www.coolfluxdsp.com. In the context of Digital Signal Processing (DSP), Philips is a founding member of DSP Valley (www.dspvalley.com), a technology networking organization grouping more than 1800 DSP engineers, headquartered in Leuven, Belgium.
About Royal Philips Electronics
Royal Philips Electronics of the Netherlands is one of the world’s biggest electronics companies and Europe’s largest, with sales of EUR 29 billion in 2003. It is a global leader in color television sets, lighting, electric shavers, medical diagnostic imaging and patient monitoring, and one-chip TV products. Its 164,300 employees in more than 60 countries are active in the areas of lighting, consumer electronics, domestic appliances, semiconductors, and medical systems. Philips is quoted on the NYSE, Amsterdam and other stock exchanges. News from Philips is located at www.philips.com/newscenter.
About Target Compiler Technologies
Target Compiler Technologies is the leading provider of retargetable software tools to accelerate the design, programming and verification of flexible processor cores, from embedded processors to programmable ASICs. Target’s Chess/Checkers tool-suite has been applied by customers worldwide to design customized cores for diverse application domains, including GSM, 3G, VoIP, audio coding, ADSL, VDSL, wireless LAN, WCDMA, hearing aids, mobile image processing and various control and interfacing applications. Target is headquartered in Leuven, Belgium, and has distribution channels in different parts of the world. Target is an IMEC spin-off and a member of the DSP Valley networking organization. Visit Target on the Internet at www.retarget.com.
Synopsys and DesignWare are registered trademarks of Synopsys, Inc.
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