Renesas Creates Virtually Soft-Error-Free Low-Power-Consumption SRAM

6/18/2004 - Renesas Technology Corp. has developed the industry's first SRAM virtually free of soft errors1, dubbed "superSRAM", through the development a new type of memory cell combining an SRAM cell with a DRAM capacitor technology. This new SRAM will be applied to, and put into commercial production for, the 16M-bit low-power SRAM for mobile applications. Details will be announced at the 2004 Symposium on VLSI Technology2 to be held in Hawaii in the United States on June 17 (local time).

The main features of the technology and product are summarized below.

(1) High soft error tolerance
An approximately 4-digit improvement in the soft error rate compared with Renesas Technology's previous 0.13 m process 16M-bit low-power SRAM (without ECC circuitry3) has been achieved by providing a cylindrical capacitor4, like the type used for DRAM cells, at each memory cell storage node5. Alpha ray radiation experiments have confirmed for the first time that the SRAM performance is free of bit defects due to soft errors. The problem of soft error tolerance, which is a fundamental issue for conventional SRAM, has been solved, enabling highly reliable, high-density SRAM to be realized.

(2) Industry's smallest memory cell size for a 0.15 m process SRAM
The development of a new type of cell that combines an SRAM cell using TFTs6 and a DRAM capacitor has resulted in the industry's smallest memory cell size for a 0.15 m process SRAM: 0.98 m2. The cell size is less than half that of Renesas Technology's current CMOS-based 0.15 m process SRAM. It will enable chip size to be greatly reduced and mobile devices to be made smaller. In addition, a data retention current of less than 1 A has been achieved. Unlike a pseudo-SRAM that employs DRAM memory cells, the new SRAM cell does not need refresh operations. That allows an approximately double-digit improvement in data retention current compared with a pseudo-SRAM, for lower power consumption in mobile applications.

(3) Fabrication possible using existing 0.15 m process
Higher performance and a smaller cell area have been achieved without using special processes. Fabrication is possible using existing process technologies, enabling early introduction to the market.

In the mobile market covering cellular phones and similar products, there is a growing demand for memory devices offering large capacity, low power consumption, and small chip size. A conventional CMOS-based SRAM is characterized by a cell area at least ten times larger than that of a DRAM using the same process rule, and has an extremely large chip area compared with a DRAM. Thus, when it is necessary to install large-capacity RAM in a small package, a pseudo-SRAM that uses DRAM memory cells and includes an SRAM interface is the normal choice. However, since pseudo-SRAM requires internal refresh operations, its standby current is larger than that of SRAM by a double-digit factor, at approximately 100 A. The RAM data retention current is an important characteristic affecting the standby time of a mobile phone, so there is a need for RAM that offers large capacity and low power consumption in a small chip size.

Although conventional SRAM has responded to the need for larger capacity through the use of advanced processes, process scaling7 also brings a reduction in the capacitance of memory cell storage nodes. This has led to the occurrence of soft errors, causing loss of information due to charges generated when the silicon substrate is irradiated with alpha or neutron rays. When lower power consumption is implemented, in particular, the lower power supply voltage results in an acceleration of the decrease in the amount of charge accumulated at storage nodes. That makes soft errors an even greater problem with regard to product reliability. Preventing this problem requires the adoption of measures such as sacrificing chip area to increase node capacitance, or the provision of ECC circuitry.

Against this backdrop, Renesas Technology carried out the development on a memory technology offering small size together with low power consumption and high reliability. Renesas Technology subsequently developed the new type of memory cell offering a smaller cell area without the need for additional complex processes and achieving high soft error tolerance while maintaining an extremely low data retention current, and has now completed commercial development of "superSRAM" 16-Mbit low-power SRAM.

Additional Development Technology and Product Information
Based on low-power-consumption SRAM technology using TFTs, in which Renesas Technology has long experience, and DRAM design technology, the company developed the new type of memory cell offering large capacitance, small size, and low power consumption, together with high soft error tolerance.

Normal SRAM cells comprise six transistors: two CMOS type load MOS transistors, two access MOS transistors, and two driver MOS transistors. In the new superSRAM, the two load MOS transistors are replaced by two TFTs located above the access MOS/driver MOS transistors, and two cylindrical capacitors are stacked on top of the node. This design achieves the industry's smallest memory cell size of 0.98 m2 for 0.15 m process SRAM. A sub-1 m2 cell size, considered to be attainable with 90 nm process nodes, has been realized, and the cell size has been reduced to less than half that of conventional Renesas Technology's 0.15 m process CMOS type SRAM.

Also, the use of DRAM cylindrical capacitors at the storage nodes has enabled capacitance to be increased compared with normal CMOS type RAM, and provides a structure in which soft errors cannot in effect occur, making it possible to provide highly reliable memory devices.

As with conventional SRAM, information stored in a memory cell is automatically maintained by means of the load transistors and driver transistors, so that there is, of course, no need for refreshing. It makes possible an approximately double-digit improvement in data retention current compared with pseudo-SRAM.

The newly developed superSRAM technology fundamentally solves the problem of soft error tolerance associated with finer SRAM processes. It has opened the way to the implementation of a highly reliable large-capacity SRAM. Following on from the 16M model, there are plans for commercial development of 32M-bit superSRAM during the current fiscal year.

1. Soft error: A transient phenomenon in memory devices whereby memory information is lost due to positive hole/electron pairs generated in the silicon substrate during alpha or neutron ray irradiation from outside sources. Tolerance increases in proportion to the amount of charge accumulated at a storage node.
2. 2004 Symposium on VLSI Technology: An International semiconductor conference to be held in Honolulu, Hawaii in U.S. from June 15 through 17, 2004.
3. ECC circuitry: For purposes of error correction, data includes code information calculated from a certain set number of bits of the data. When the data is read, ECC circuitry performs the calculation again and checks whether the data has been corrupted. In the case of data using an 8-bit ECC length, for example, errors can be detected for up to two original data bits, and a 1-bit error can be corrected.
4. Cylindrical capacitor: A capacitor used in DRAM with two electrodes formed of polysilicon or metal. The capacitor is formed in a higher layer than the silicon substrate, and is effective in reducing the memory cell area.
5. Storage node: The place in a memory cell at which information is stored as a potential
6. TFT (Thin Film Transistor): A transistor in which thin-film polysilicon formed on an insulating film forms the substrate. Renesas Technology has SRAM in mass production using TFTs as load transistors.
7. Scaling: A higher degree of integration and higher performance can be attained for MOS devices by miniaturizing an MOS device three-dimensionally, and systematically changing the power supply voltage and impurity concentration at the same time. This MOS device miniaturization is called scaling.

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