6/8/2004 - Cadence Design Systems, Inc. (NYSE: CDN) announced Cadence® First Encounter® Global Physical Synthesis (GPS), a new product that integrates silicon virtual prototyping and second-generation global physical synthesis technology into a single environment. With First Encounter GPS, designers can create much larger chips than was practical with older methods. The new technology completes the Cadence Encounter digital IC design platform’s core technology portfolio in the Encounter 4.1 release.
First Encounter GPS leverages Cadence RTL Compiler’s global-focused synthesis for speed and capacity and Quality of Silicon (QoS). Unlike first-generation physical synthesis approaches that optimise a single logic path at a time, global physical synthesis optimises timing for many paths concurrently. This dramatically reduces the compute effort needed for design convergence and enables silicon success even on very large blocks in short design schedules. First Encounter GPS supports both RTL-to-placed gates and netlist-to-placed gates design styles.
“Very large SoC designs are becoming difficult to complete using block sizes of 1 or 2 million gates,” said Hisaharu Miwa, department manager of the EDA Technology Development Dept. at Renesas Technology Corp. “The chips must be divided into so many blocks that assembly becomes impractical. First Encounter GPS enables practical design closure on larger block sizes that we would not even have tried in the past. It changes how we look at large-scale SoC design.”
“The ability to close timing within the prototyping phase is a major productivity improvement for us,” said Yoshito Muraishi, Senior Manager, CAD System Backend, Products Development & Design Dept. of Kawasaki Microelectronics, Inc. “We’ve been very impressed with how quickly First Encounter GPS reaches timing closure. Using First Encounter GPS we observe up to 2x turn around time improvements for our designs.”
“We’re extremely pleased with how quickly First Encounter GPS reaches timing closure on large blocks,” said Li-Siang Lee, physical design manager at Cortina. “Its capacity and performance allow us to tackle tasks we would not otherwise have attempted, which in turn will make it easier to scale our designs to very large gate counts.”
“First Encounter GPS has been used to tape out flat blocks from 3 to 8 million gates in hours instead of days,” said Lavi Lev, Cadence executive vice president and general manager. “With First Encounter GPS, the Encounter platform provides the entire system, including synthesis, silicon virtual prototyping, physical synthesis, routing and signal integrity, for the new generation of large-scale system-on-chip design. This gives designers the speed they need to meet tight time-to-market windows.”
Cadence is the largest supplier of electronic design technologies and engineering services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centres, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks and Encounter, SoC Encounter and NanoRoute are trademarks of Cadence Design Systems, Inc.
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