6/8/2004 - Celoxica announced advanced synthesis technology for the SystemC language. Celoxica’s new Agility Compiler synthesises SystemC directly to high-density FPGA and Programmable SoC logic and generates RTL VHDL and Verilog for SoC design.
The Agility Compiler takes in SystemC and outputs optimised EDIF netlists for high-density programmable logic devices from Actel, Altera Corp. and Xilinx. The Agility Compiler also generates VHDL and Verilog RTL output to support SoC synthesis tools. Integrated with Celoxica’s popular DK Design Suite of tools for co-design and co-verification, the Agility Compiler extends the benefits of Software-Compiled System Design to users of SystemC.
"Celoxica, the inventor of algorithm to FPGA and RTL compilation via Handel-C, has the most industry experience in developing synthesis tools from C-based languages. The Agility Compiler extends this capability to SystemC and confirms Celoxica’s position as the leading provider of C synthesis solutions," said Phil Bishop president and CEO of Celoxica.
A member of Open SystemC Initiative (OSCI), Celoxica is applying the experience and acumen of a worldwide customer base and over 10 years experience in delivering C-based synthesis to the development of this SystemC implementation solution. "The critical gap in SystemC design has been the route to silicon," said Jeff Jussel, vice president marketing for Celoxica. "By bridging the gap between design idea and product reality we’ve addressed one of the major bottlenecks to SystemC adoption and enabled companies to realise a return on investment in their SystemC modelling, design and verification efforts."
FPGA and Programmable SoC designers using SystemC can use the Agility Compiler to maintain the C level of design abstraction throughout the entire SystemC design process. Users can take advantage of simulation speeds that are orders of magnitude faster than RTL, and whole systems can now be verified using the same test-bench at all stages of the design process. The Agility Compiler also allows users to avoid the lengthy manual translations of SystemC models to RTL that break the verification flow and introduce new errors. By gaining full confidence in the integrity of the final design against the system specification, design productivity can be increased and the verification overhead reduced.
"By working with Celoxica to provide SystemC synthesis for Actel’s FPGAs, including its flash-based ProASIC Plus family, we are broadening the design base for our solutions and supporting an important emerging design standard," said Yankin Tanurhan, senior director, applications and IP solutions at Actel. "Using the Agility Compiler, our customers can easily implement a wide range of intellectual property cores to develop highly differentiated products for consumer, automotive, and military and aerospace markets."
Developed using Celoxica’s advanced synthesis algorithms and optimisation technology, the Agility Compiler is designed to meet the growing demand from SystemC users for high-level synthesis solutions. The tool efficiently compiles synthesisable SystemC and utilizes available resources on the targeted device to produce efficient hardware implementations.
"The adoption of ESL design requires the application of new languages to complement the way designers currently think and work," said Joe Hanson Altera marketing director for system-level development tools. "Celoxica’s Handel-C provides a quick path from algorithm to FPGA within the Altera SOPC Builder flow. The availability of the Agility Compiler will extend that system design capability to customers who intend to use SystemC."
The Agility Compiler is the optimum balance between design automation and designer control removing the burden and risk of error-prone, stepwise hand refinement of SystemC models to synthesisable descriptions.
"Xilinx FPGAs are constantly pushing the envelope in device density. SystemC is a standard which is gaining traction for the modelling and verification of multi-million gate designs," said Steve Lass, director of software product marketing at Xilinx. "With the introduction of the Agility Compiler, Celoxica is providing the capability to implement those designs in an FPGA, avoiding the time consuming task of manually converting to VHDL or Verilog."
In addition to the SystemC language Celoxica continues to provide comprehensive support for the Handel-C language, focused on Image Processing and DSP design in high-end Programmable Logic and Programmable SoC devices.
"With 300+ and growing customers using our Handel-C product, commitment to the language and continued tool development is solid. For too long the ESL (Electronic System Level) design debate has focused upon which language customers should or should not use and this has distracted attention and effort from the real issue of creating a comprehensive flow and methodology that truly enables ESL design," said Phil Bishop, CEO of Celoxica "I believe our announcement today is the critical step in delivering the promise of system level design by providing the interoperability between different languages and tools that are necessary at different stages within ESL."
An innovator in system-level electronic design automation (EDA), Celoxica supplies the design technology, IP and services that define Software-Compiled System Design, a methodology that exploits higher levels of design abstraction to dramatically improve silicon design productivity. Celoxica’s products address hardware/software partitioning, co-verification and C-based synthesis to reconfigurable hardware. Established in 1996, Celoxica offers a proven route from complex software algorithms to hardware, and provides an ideal design environment for System FPGA with significant productivity advantages for digital signal processing applications such as imaging, electronic security and communications.
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