0-In's Archer Verification System Supports SystemVerilog and VHDL

6/8/2004 - 0-In Design Automation, the Assertion-Based Verification Company, announced products within the Archer Verification system that provide support for Accellera's SystemVerilog 3.1a design constructs and IEEE-1076 VHDL. These new products join 0-In's already strong support of standard languages that include IEEE-1364 Verilog and Accellera's Property Specification Language (PSL).

"0-In is actively and firmly committed to open standards and interoperability", said Steve White, 0-In's president and CEO, "Our customer base, with over 15,000 assertion simulation licenses and 5,000 formal verification licenses, continues to help us prioritize rollout of standards support. Now customers using SystemVerilog and VHDL will have access to the industry's most widely used tools and proven methodologies for reaching verification closure."

Archer-CDV will support SystemVerilog 3.1a design constructs and VHDL to provide structural and assertion-based coverage capabilities within a coverage-driven verification methodology. Archer-CDV leverages 0-In's CheckerWare® library of assertions and monitors to detect bugs earlier and make debug faster. CheckerWare encapsulates both functional checking and structural coverage monitoring for testing common design elements and standard interfaces.

Archer-SF will support VHDL to provide design teams with an easy-to-use, powerful static assertion-based and formal verification capability for finding bugs. Archer-SF includes automatic RTL rule checking, static clock-domain crossing verification and static formal verification of assertions.

Pricing and Availability
Archer-CDV has a North American list price of $50,000 for a one-year time-based license. Archer-CDV with SystemVerilog 3.1a design constructs and VHDL support is available for early-access customers now and will be generally available in the fourth quarter of 2004. Archer-SF has a North American list price of $60,000 for a one-year time-based license. Archer-SF with VHDL support is available for early-access customers now and will be generally available in the fourth quarter of 2004.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution built on industry standards that provides value throughout the design and verification cycle - from the block level to the chip and system levels. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

0-In® and CheckerWare® and Archer VerificationTM are trademarks or registered trademarks of 0-In Design Automation, Inc.

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