Altera Discusses Current Design Alternatives at DAC
6/8/2004 - Altera participates in "ASIC, COT or FPGA: Which Should Your Next Chip Be?" panel, which will take place Thursday, June 10, from 10:15 a.m. to 11:00 a.m. in the DAC Pavilion on the exhibit floor. Altera will be represented on this panel by Robert Blake, vice president of product planning. Blake will compare and contrast the design costs and challenges involved in implementing designs in FPGAs and ASICs.
In addition, Altera will be conducting joint product demonstrations and presentations in the booths of a number of its EDA partners, including Cadence, Celoxica, Mentor, Synopsys and Synplicity. These demonstrations will highlight the benefits engineers can gain from using the tools of these leading EDA vendors to implement their designs in Altera FPGAs.
Panel: ASIC, COT, or FPGA: Which Should Your Next Chip Be?
Speaker: Robert Blake, Vice President, Product Planning, Altera
Thursday, June 10
10:15 a.m. – 11:00 a.m.
Room: DAC Pavilion, Exhibit Floor
DAC 2004
June 7-11, 2004
San Diego Convention Center
111 W. Harbor Dr.
San Diego, CA 92101
For Additional Information:
www.dac.com/41st/index.html
Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.
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