Sequence Design Hosts Panel on Reducing Leakage Power at DAC

6/7/2004 - Sequence Design will host DAC '04 panel on methods to reduce leakage power on Monday June 7 from 12-2PM.

Design Automation Conference
San Diego Convention Center, Room 22
Seats are limited, so please RSVP at:



"Will (C)MOS Grow Before Leakage is Licked?"
Transistor leakage has become a critical design issue with present generation process technologies. Every indication is that leakage will become significantly more challenging with each new process generation. Circuit designers, process developers and EDA tool providers are beginning to develop solutions to the leakage problem, a number of approaches have already been proposed and studied. These include non-traditional device structures such as FinFETs and new or modified design techniques such as MTCMOS and VTCMOS. But deploying any of these solutions raises new questions that will be explored in this panel session.

About Sequence
Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 130 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 10 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Additional information is available at

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