6/7/2004 - Sequence Design announced the new release of PhysicalStudio with "physical power" features that reduce power consumption -- and simultaneously preserve timing and signal integrity design objectives. Physical power features include leakage power optimization for multi-Vt libraries.
PhysicalStudio's physical power optimization reduces dynamic and leakage power. Using PhysicalStudio, designers can concurrently optimize for power, voltage drop, timing and signal integrity, thereby ensuring the electrical integrity of the design.
Designers have already experienced the benefits of using Sequence's leakage power capabilities. "Physical Studio employs optimization methods for leakage power reduction that were developed in collaboration with NVIDIA," said Calist Friedman, VLSI design engineer at NVIDIA. "The results are quite impressive, we have achieved greater than a 30% reduction in leakage power."
Sequence has been an innovator in the area of leakage power reduction beginning with the company's technology partnership with Toshiba through its success with NVIDIA's GForceFX designs. This release of PhysicalStudio 2004.2 adds leakage power optimization for multi-Vt libraries available from Sequence partners like Artisan Components.
Reducing Leakage Power Becomes Critical
Power is a major concern for all SoC designers. Leakage power, which was negligible in 180-nm processes, can be as high as 30 percent of the total power consumption in 130-nm designs and 60% in 90-nm designs. It needs to be analyzed and optimized in context of timing and signal integrity.
A high-level of optimization accuracy is required to increase confidence at the sign-off stage in the design cycle. PhysicalStudio contains chip-level timing and signal integrity optimization using Periphery Netlist Models (PNM(TM)) for sub-blocks that results in sign-off quality accuracy for designs with 10 to 100 million gates.
The specific power reductions that Physical Studio uses to trade-off slack timing for power are cell resizing and multi-threshold-voltage (Vt) cell swapping. Cells employing a high Vt threshold implant, resulting in reduced leakage despite longer delays, are substituted for low Vt cells wherever timing slack permits where power management is the priority. The swapping is reversed where timing is the priority.
Unlike simplistic dual-Vt (2 threshold levels) cell swapping techniques in other physical implementation tools, PhysicalStudio can handle multiple (greater than 2) threshold levels while preventing setup, hold, maxtrans and maxcap violations. The advanced algorithms in PhysicalStudio are topologically sensitive to prevent timing degradation and cell swapping in heavily congested areas. The resulting optimization maximizes leakage power reduction while maintaining electrical integrity, hence minimizing the number of design and analysis iterations.
"Multi-threshold optimization and power gating will be essential components of the preferred leakage solution. They can be deployed on standard processes and have a low design automation cost," said Scott Becker, CTO at Artisan. "We look forward to combining our expertise with Sequence's in developing power gating and signal-integrity technology solutions."
The demand for tools that optimize for leakage power is increasing dramatically. "PhysicalStudio is becoming a robust IC implementation engine, production proven on more than 130 tapeouts and on the most notable leading-edge designs in the marketplace," said Vic Kulkarni, president and CEO of Sequence Design. "Optimizing for leakage power is one of the most significant benefits Sequence can offer designers. The ROI for our customers includes extended battery life, reduced packaging costs and lower manufacturing costs due to reduced metal layers."
Additional New Features in PhysicalStudio 2004.2
The current release of PhysicalStudio also includes the following features:
The product is available on the following platforms: Linux 64-bit Itanium and Opteron; Sun Solaris 64-bit.
DAC '04 Demos
PhysicalStudio will be demonstrated from June 7-10, 2004 in booth 2107 at the Design Automation Conference in the San Diego Convention Center. The demonstrations will also feature Artisan IP. To register, please visit: http://www.sequencedesign.com/3_news/query-form.html
For more information on Sequence's leakage power partnership with Toshiba on MTCMOS, please see: http://subscriber.acumeninfo.com/uploads/7A193D0CA31FAFF58196DA6D6723C960/1067965516395/SOURCE/sequence.html
PhysicalStudio leverages Sequence experience in low-power design tools as part of the company's NanoCool(TM) Initiative. NanoCool is a joint venture among semiconductor designers, EDA tool vendors, IP companies and library suppliers, to provide a complete power integrity flow that includes concurrent power management, timing and signal-integrity capabilities to achieve rapid design closure at 130-nm and below.
Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 130 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.
Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 10 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Additional information is available at sequencedesign.com.
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